From nobody Wed Apr 16 13:38:53 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1534273195468423.2411591656436; Tue, 14 Aug 2018 11:59:55 -0700 (PDT) Received: from localhost ([::1]:45815 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fpeXq-0001ML-9t for importer@patchew.org; Tue, 14 Aug 2018 14:59:54 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52589) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fpdvL-0004ml-22 for qemu-devel@nongnu.org; Tue, 14 Aug 2018 14:21:47 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fpdtz-0006g6-8j for qemu-devel@nongnu.org; Tue, 14 Aug 2018 14:20:06 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:44414) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fpdty-0006eo-Vz for qemu-devel@nongnu.org; Tue, 14 Aug 2018 14:18:43 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fpdtx-0007GR-Mx for qemu-devel@nongnu.org; Tue, 14 Aug 2018 19:18:41 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 14 Aug 2018 19:17:51 +0100 Message-Id: <20180814181815.23348-22-peter.maydell@linaro.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180814181815.23348-1-peter.maydell@linaro.org> References: <20180814181815.23348-1-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 21/45] intc/arm_gic: Implement virtualization extensions in gic_(activate_irq|drop_prio) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RDMRC_1 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Luc Michel Implement virtualization extensions in gic_activate_irq() and gic_drop_prio() and in gic_get_prio_from_apr_bits() called by gic_drop_prio(). When the current CPU is a vCPU: - Use GIC_VIRT_MIN_BPR and GIC_VIRT_NR_APRS instead of their non-virt counterparts, - the vCPU APR is stored in the virtual interface, in h_apr. Signed-off-by: Luc Michel Reviewed-by: Peter Maydell Message-id: 20180727095421.386-11-luc.michel@greensocs.com Signed-off-by: Peter Maydell --- hw/intc/arm_gic.c | 50 +++++++++++++++++++++++++++++++++++------------ 1 file changed, 38 insertions(+), 12 deletions(-) diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index 26ed7ea58ab..de73dc9f54b 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -276,16 +276,23 @@ static void gic_activate_irq(GICState *s, int cpu, in= t irq) * and update the running priority. */ int prio =3D gic_get_group_priority(s, cpu, irq); - int preemption_level =3D prio >> (GIC_MIN_BPR + 1); + int min_bpr =3D gic_is_vcpu(cpu) ? GIC_VIRT_MIN_BPR : GIC_MIN_BPR; + int preemption_level =3D prio >> (min_bpr + 1); int regno =3D preemption_level / 32; int bitno =3D preemption_level % 32; + uint32_t *papr =3D NULL; =20 - if (gic_has_groups(s) && gic_test_group(s, irq, cpu)) { - s->nsapr[regno][cpu] |=3D (1 << bitno); + if (gic_is_vcpu(cpu)) { + assert(regno =3D=3D 0); + papr =3D &s->h_apr[gic_get_vcpu_real_id(cpu)]; + } else if (gic_has_groups(s) && gic_test_group(s, irq, cpu)) { + papr =3D &s->nsapr[regno][cpu]; } else { - s->apr[regno][cpu] |=3D (1 << bitno); + papr =3D &s->apr[regno][cpu]; } =20 + *papr |=3D (1 << bitno); + s->running_priority[cpu] =3D prio; gic_set_active(s, irq, cpu); } @@ -296,6 +303,16 @@ static int gic_get_prio_from_apr_bits(GICState *s, int= cpu) * on the set bits in the Active Priority Registers. */ int i; + + if (gic_is_vcpu(cpu)) { + uint32_t apr =3D s->h_apr[gic_get_vcpu_real_id(cpu)]; + if (apr) { + return ctz32(apr) << (GIC_VIRT_MIN_BPR + 1); + } else { + return 0x100; + } + } + for (i =3D 0; i < GIC_NR_APRS; i++) { uint32_t apr =3D s->apr[i][cpu] | s->nsapr[i][cpu]; if (!apr) { @@ -324,16 +341,25 @@ static void gic_drop_prio(GICState *s, int cpu, int g= roup) * running priority will be wrong, so interrupts that should preempt * might not do so, and interrupts that should not preempt might do so. */ - int i; + if (gic_is_vcpu(cpu)) { + int rcpu =3D gic_get_vcpu_real_id(cpu); =20 - for (i =3D 0; i < GIC_NR_APRS; i++) { - uint32_t *papr =3D group ? &s->nsapr[i][cpu] : &s->apr[i][cpu]; - if (!*papr) { - continue; + if (s->h_apr[rcpu]) { + /* Clear lowest set bit */ + s->h_apr[rcpu] &=3D s->h_apr[rcpu] - 1; + } + } else { + int i; + + for (i =3D 0; i < GIC_NR_APRS; i++) { + uint32_t *papr =3D group ? &s->nsapr[i][cpu] : &s->apr[i][cpu]; + if (!*papr) { + continue; + } + /* Clear lowest set bit */ + *papr &=3D *papr - 1; + break; } - /* Clear lowest set bit */ - *papr &=3D *papr - 1; - break; } =20 s->running_priority[cpu] =3D gic_get_prio_from_apr_bits(s, cpu); --=20 2.18.0