From nobody Mon Feb 9 00:27:02 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 153427256906581.3662603533802; Tue, 14 Aug 2018 11:49:29 -0700 (PDT) Received: from localhost ([::1]:45758 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fpeNj-0005rS-TV for importer@patchew.org; Tue, 14 Aug 2018 14:49:27 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52552) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fpdvG-0004iy-US for qemu-devel@nongnu.org; Tue, 14 Aug 2018 14:21:44 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fpdtv-0006eZ-T6 for qemu-devel@nongnu.org; Tue, 14 Aug 2018 14:20:02 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:44408) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fpdtv-0006ag-7g for qemu-devel@nongnu.org; Tue, 14 Aug 2018 14:18:39 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fpdtp-0007Cl-6O for qemu-devel@nongnu.org; Tue, 14 Aug 2018 19:18:33 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Tue, 14 Aug 2018 19:17:43 +0100 Message-Id: <20180814181815.23348-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180814181815.23348-1-peter.maydell@linaro.org> References: <20180814181815.23348-1-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PULL 13/45] intc/arm_gic: Implement GICD_ISACTIVERn and GICD_ICACTIVERn registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RDMRC_1 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Luc Michel Implement GICD_ISACTIVERn and GICD_ICACTIVERn registers in the GICv2. Those registers allow to set or clear the active state of an IRQ in the distributor. Signed-off-by: Luc Michel Reviewed-by: Peter Maydell Message-id: 20180727095421.386-3-luc.michel@greensocs.com Signed-off-by: Peter Maydell --- hw/intc/arm_gic.c | 61 +++++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 57 insertions(+), 4 deletions(-) diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index 9286236d86b..53b749d2167 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -725,8 +725,16 @@ static uint32_t gic_dist_readb(void *opaque, hwaddr of= fset, MemTxAttrs attrs) } } } else if (offset < 0x400) { - /* Interrupt Active. */ - irq =3D (offset - 0x300) * 8 + GIC_BASE_IRQ; + /* Interrupt Set/Clear Active. */ + if (offset < 0x380) { + irq =3D (offset - 0x300) * 8; + } else if (s->revision =3D=3D 2) { + irq =3D (offset - 0x380) * 8; + } else { + goto bad_reg; + } + + irq +=3D GIC_BASE_IRQ; if (irq >=3D s->num_irq) goto bad_reg; res =3D 0; @@ -1007,9 +1015,54 @@ static void gic_dist_writeb(void *opaque, hwaddr off= set, GIC_DIST_CLEAR_PENDING(irq + i, ALL_CPU_MASK); } } + } else if (offset < 0x380) { + /* Interrupt Set Active. */ + if (s->revision !=3D 2) { + goto bad_reg; + } + + irq =3D (offset - 0x300) * 8 + GIC_BASE_IRQ; + if (irq >=3D s->num_irq) { + goto bad_reg; + } + + /* This register is banked per-cpu for PPIs */ + int cm =3D irq < GIC_INTERNAL ? (1 << cpu) : ALL_CPU_MASK; + + for (i =3D 0; i < 8; i++) { + if (s->security_extn && !attrs.secure && + !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) { + continue; /* Ignore Non-secure access of Group0 IRQ */ + } + + if (value & (1 << i)) { + GIC_DIST_SET_ACTIVE(irq + i, cm); + } + } } else if (offset < 0x400) { - /* Interrupt Active. */ - goto bad_reg; + /* Interrupt Clear Active. */ + if (s->revision !=3D 2) { + goto bad_reg; + } + + irq =3D (offset - 0x380) * 8 + GIC_BASE_IRQ; + if (irq >=3D s->num_irq) { + goto bad_reg; + } + + /* This register is banked per-cpu for PPIs */ + int cm =3D irq < GIC_INTERNAL ? (1 << cpu) : ALL_CPU_MASK; + + for (i =3D 0; i < 8; i++) { + if (s->security_extn && !attrs.secure && + !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) { + continue; /* Ignore Non-secure access of Group0 IRQ */ + } + + if (value & (1 << i)) { + GIC_DIST_CLEAR_ACTIVE(irq + i, cm); + } + } } else if (offset < 0x800) { /* Interrupt Priority. */ irq =3D (offset - 0x400) + GIC_BASE_IRQ; --=20 2.18.0