From nobody Wed Nov 5 13:30:18 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1534250892925978.1882830721332; Tue, 14 Aug 2018 05:48:12 -0700 (PDT) Received: from localhost ([::1]:44188 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fpYk7-0000zE-T1 for importer@patchew.org; Tue, 14 Aug 2018 08:48:11 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43785) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fpYfH-0005VO-UN for qemu-devel@nongnu.org; Tue, 14 Aug 2018 08:43:13 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fpYfG-0002IO-SB for qemu-devel@nongnu.org; Tue, 14 Aug 2018 08:43:11 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:44302) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fpYfE-0001z2-I0; Tue, 14 Aug 2018 08:43:08 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fpYfC-0006q5-M7; Tue, 14 Aug 2018 13:43:06 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 14 Aug 2018 13:42:50 +0100 Message-Id: <20180814124254.5229-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180814124254.5229-1-peter.maydell@linaro.org> References: <20180814124254.5229-1-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH 06/10] target/arm: Implement AArch32 Hyp FARs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgari@xilinx.com, Luc Michel , patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RDMRC_1 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The AArch32 virtualization extensions support these fault address registers: * HDFAR: aliased with AArch64 FAR_EL2[31:0] and AArch32 DFAR(S) * HIFAR: aliased with AArch64 FAR_EL2[63:32] and AArch32 IFAR(S) Implement the accessors for these. This fixes in passing a bug where we weren't implementing the "RES0 from EL3 if EL2 not implemented" behaviour for AArch64 FAR_EL2. Signed-off-by: Peter Maydell Reviewed-By: Luc Michel Reviewed-by: Edgar E. Iglesias --- target/arm/helper.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 9701e413859..d6e98e9d606 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3847,6 +3847,13 @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = =3D { { .name =3D "HSTR_EL2", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 3, .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "FAR_EL2", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 6, .crm =3D 0, .opc2 =3D 0, + .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "HIFAR", .state =3D ARM_CP_STATE_AA32, + .type =3D ARM_CP_CONST, + .cp =3D 15, .opc1 =3D 4, .crn =3D 6, .crm =3D 0, .opc2 =3D 2, + .access =3D PL2_RW, .resetvalue =3D 0 }, REGINFO_SENTINEL }; =20 @@ -3922,9 +3929,14 @@ static const ARMCPRegInfo el2_cp_reginfo[] =3D { { .name =3D "ESR_EL2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 5, .crm =3D 2, .opc2 =3D 0, .access =3D PL2_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.esr_= el[2]) }, - { .name =3D "FAR_EL2", .state =3D ARM_CP_STATE_AA64, + { .name =3D "FAR_EL2", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 6, .crm =3D 0, .opc2 =3D 0, .access =3D PL2_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.far_= el[2]) }, + { .name =3D "HIFAR", .state =3D ARM_CP_STATE_AA32, + .type =3D ARM_CP_ALIAS, + .cp =3D 15, .opc1 =3D 4, .crn =3D 6, .crm =3D 0, .opc2 =3D 2, + .access =3D PL2_RW, + .fieldoffset =3D offsetofhigh32(CPUARMState, cp15.far_el[2]) }, { .name =3D "SPSR_EL2", .state =3D ARM_CP_STATE_AA64, .type =3D ARM_CP_ALIAS, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 4, .crm =3D 0, .opc2 =3D 0, --=20 2.18.0