From nobody Mon Feb 9 03:57:21 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1534250789729939.2271785207012; Tue, 14 Aug 2018 05:46:29 -0700 (PDT) Received: from localhost ([::1]:44175 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fpYiR-0007yB-9R for importer@patchew.org; Tue, 14 Aug 2018 08:46:27 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43892) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fpYfK-0005Yd-Dz for qemu-devel@nongnu.org; Tue, 14 Aug 2018 08:43:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fpYfJ-0002NE-Cb for qemu-devel@nongnu.org; Tue, 14 Aug 2018 08:43:14 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:44302) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fpYfG-0001z2-GB; Tue, 14 Aug 2018 08:43:10 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fpYfB-0006pY-Na; Tue, 14 Aug 2018 13:43:05 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 14 Aug 2018 13:42:49 +0100 Message-Id: <20180814124254.5229-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180814124254.5229-1-peter.maydell@linaro.org> References: <20180814124254.5229-1-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH 05/10] target/arm: Implement AArch32 HCR and HCR2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgari@xilinx.com, Luc Michel , patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RDMRC_1 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The AArch32 HCR and HCR2 registers alias HCR_EL2 bits [31:0] and [63:32]; implement them. Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias --- target/arm/helper.c | 39 +++++++++++++++++++++++++++++++++++---- 1 file changed, 35 insertions(+), 4 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index b6412fe9d1f..9701e413859 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3754,11 +3754,15 @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = =3D { .opc0 =3D 3, .opc1 =3D 4, .crn =3D 12, .crm =3D 0, .opc2 =3D 0, .access =3D PL2_RW, .readfn =3D arm_cp_read_zero, .writefn =3D arm_cp_write_ignore }, - { .name =3D "HCR_EL2", .state =3D ARM_CP_STATE_AA64, + { .name =3D "HCR_EL2", .state =3D ARM_CP_STATE_BOTH, .type =3D ARM_CP_NO_RAW, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 0, .access =3D PL2_RW, - .readfn =3D arm_cp_read_zero, .writefn =3D arm_cp_write_ignore }, + .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "HCR2", .state =3D ARM_CP_STATE_AA32, + .cp =3D 15, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 4, + .access =3D PL2_RW, + .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, { .name =3D "CPTR_EL2", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 2, .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, @@ -3872,10 +3876,26 @@ static void hcr_write(CPUARMState *env, const ARMCP= RegInfo *ri, uint64_t value) * HCR_PTW forbids certain page-table setups * HCR_DC Disables stage1 and enables stage2 translation */ - if ((raw_read(env, ri) ^ value) & (HCR_VM | HCR_PTW | HCR_DC)) { + if ((env->cp15.hcr_el2 ^ value) & (HCR_VM | HCR_PTW | HCR_DC)) { tlb_flush(CPU(cpu)); } - raw_write(env, ri, value); + env->cp15.hcr_el2 =3D value; +} + +static void hcr_writehigh(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + /* Handle HCR2 write, i.e. write to high half of HCR_EL2 */ + value =3D deposit64(env->cp15.hcr_el2, 32, 32, value); + hcr_write(env, NULL, value); +} + +static void hcr_writelow(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + /* Handle HCR write, i.e. write to low half of HCR_EL2 */ + value =3D deposit64(env->cp15.hcr_el2, 0, 32, value); + hcr_write(env, NULL, value); } =20 static const ARMCPRegInfo el2_cp_reginfo[] =3D { @@ -3883,6 +3903,17 @@ static const ARMCPRegInfo el2_cp_reginfo[] =3D { .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 0, .access =3D PL2_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.hcr_= el2), .writefn =3D hcr_write }, + { .name =3D "HCR", .state =3D ARM_CP_STATE_AA32, + .type =3D ARM_CP_ALIAS, + .cp =3D 15, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 0, + .access =3D PL2_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.hcr_= el2), + .writefn =3D hcr_writelow }, + { .name =3D "HCR2", .state =3D ARM_CP_STATE_AA32, + .type =3D ARM_CP_ALIAS, + .cp =3D 15, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 4, + .access =3D PL2_RW, + .fieldoffset =3D offsetofhigh32(CPUARMState, cp15.hcr_el2), + .writefn =3D hcr_writehigh }, { .name =3D "ELR_EL2", .state =3D ARM_CP_STATE_AA64, .type =3D ARM_CP_ALIAS, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 4, .crm =3D 0, .opc2 =3D 1, --=20 2.18.0