From nobody Wed Nov 5 13:30:16 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1534251073961596.0921953859674; Tue, 14 Aug 2018 05:51:13 -0700 (PDT) Received: from localhost ([::1]:44205 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fpYmx-0003AQ-AY for importer@patchew.org; Tue, 14 Aug 2018 08:51:07 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43937) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fpYfL-0005ag-VN for qemu-devel@nongnu.org; Tue, 14 Aug 2018 08:43:16 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fpYfL-0002QW-1z for qemu-devel@nongnu.org; Tue, 14 Aug 2018 08:43:15 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:44302) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fpYfI-0001z2-FG; Tue, 14 Aug 2018 08:43:12 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fpYf7-0006nt-5Q; Tue, 14 Aug 2018 13:43:01 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 14 Aug 2018 13:42:46 +0100 Message-Id: <20180814124254.5229-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180814124254.5229-1-peter.maydell@linaro.org> References: <20180814124254.5229-1-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH 02/10] target/arm: Add missing .cp = 15 to HMAIR1 and HAMAIR1 regdefs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgari@xilinx.com, Luc Michel , patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RDMRC_1 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" ARMCPRegInfo structs will not default to .cp =3D 15 if they are ARM_CP_STATE_BOTH, but not if they are ARM_CP_STATE_AA32 (because a coprocessor number of 0 is valid for AArch32). We forgot to explicitly set .cp =3D 15 for the HMAIR1 and HAMAIR1 regdefs, which meant they would UNDEF when the guest tried to access them under cp15. Signed-off-by: Peter Maydell Reviewed-By: Luc Michel Reviewed-by: Edgar E. Iglesias --- A quick grep suggests these are the only ones we got wrong. --- target/arm/helper.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 2c5e02c0b1a..466c8ae492e 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3767,14 +3767,14 @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = =3D { .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, { .name =3D "HMAIR1", .state =3D ARM_CP_STATE_AA32, - .opc1 =3D 4, .crn =3D 10, .crm =3D 2, .opc2 =3D 1, + .cp =3D 15, .opc1 =3D 4, .crn =3D 10, .crm =3D 2, .opc2 =3D 1, .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, { .name =3D "AMAIR_EL2", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 10, .crm =3D 3, .opc2 =3D 0, .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, { .name =3D "HAMAIR1", .state =3D ARM_CP_STATE_AA32, - .opc1 =3D 4, .crn =3D 10, .crm =3D 3, .opc2 =3D 1, + .cp =3D 15, .opc1 =3D 4, .crn =3D 10, .crm =3D 3, .opc2 =3D 1, .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, { .name =3D "AFSR0_EL2", .state =3D ARM_CP_STATE_BOTH, @@ -3917,7 +3917,7 @@ static const ARMCPRegInfo el2_cp_reginfo[] =3D { .access =3D PL2_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.mair= _el[2]), .resetvalue =3D 0 }, { .name =3D "HMAIR1", .state =3D ARM_CP_STATE_AA32, - .opc1 =3D 4, .crn =3D 10, .crm =3D 2, .opc2 =3D 1, + .cp =3D 15, .opc1 =3D 4, .crn =3D 10, .crm =3D 2, .opc2 =3D 1, .access =3D PL2_RW, .type =3D ARM_CP_ALIAS, .fieldoffset =3D offsetofhigh32(CPUARMState, cp15.mair_el[2]) }, { .name =3D "AMAIR_EL2", .state =3D ARM_CP_STATE_BOTH, @@ -3926,7 +3926,7 @@ static const ARMCPRegInfo el2_cp_reginfo[] =3D { .resetvalue =3D 0 }, /* HAMAIR1 is mapped to AMAIR_EL2[63:32] */ { .name =3D "HAMAIR1", .state =3D ARM_CP_STATE_AA32, - .opc1 =3D 4, .crn =3D 10, .crm =3D 3, .opc2 =3D 1, + .cp =3D 15, .opc1 =3D 4, .crn =3D 10, .crm =3D 3, .opc2 =3D 1, .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, { .name =3D "AFSR0_EL2", .state =3D ARM_CP_STATE_BOTH, --=20 2.18.0