From nobody Wed Nov 5 10:58:05 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1534251223244976.3159703699783; Tue, 14 Aug 2018 05:53:43 -0700 (PDT) Received: from localhost ([::1]:44216 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fpYpS-000640-4B for importer@patchew.org; Tue, 14 Aug 2018 08:53:42 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43927) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fpYfL-0005aF-J3 for qemu-devel@nongnu.org; Tue, 14 Aug 2018 08:43:16 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fpYfK-0002Q6-Q3 for qemu-devel@nongnu.org; Tue, 14 Aug 2018 08:43:15 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:44346) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fpYfI-0002IZ-GR; Tue, 14 Aug 2018 08:43:12 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fpYf6-0006nZ-64; Tue, 14 Aug 2018 13:43:00 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 14 Aug 2018 13:42:45 +0100 Message-Id: <20180814124254.5229-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180814124254.5229-1-peter.maydell@linaro.org> References: <20180814124254.5229-1-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH 01/10] target/arm: Correct typo in HAMAIR1 regdef name X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgari@xilinx.com, Luc Michel , patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RDMRC_1 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" We implement the HAMAIR1 register as RAZ/WI; we had a typo in the regdef, though, and were incorrectly naming it HMAIR1 (which is a different register which we also implement as RAZ/WI). Signed-off-by: Peter Maydell Reviewed-By: Luc Michel Reviewed-by: Edgar E. Iglesias --- target/arm/helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 8b07bf214ec..2c5e02c0b1a 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3773,7 +3773,7 @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] =3D= { .opc0 =3D 3, .opc1 =3D 4, .crn =3D 10, .crm =3D 3, .opc2 =3D 0, .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "HMAIR1", .state =3D ARM_CP_STATE_AA32, + { .name =3D "HAMAIR1", .state =3D ARM_CP_STATE_AA32, .opc1 =3D 4, .crn =3D 10, .crm =3D 3, .opc2 =3D 1, .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, @@ -3925,7 +3925,7 @@ static const ARMCPRegInfo el2_cp_reginfo[] =3D { .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, /* HAMAIR1 is mapped to AMAIR_EL2[63:32] */ - { .name =3D "HMAIR1", .state =3D ARM_CP_STATE_AA32, + { .name =3D "HAMAIR1", .state =3D ARM_CP_STATE_AA32, .opc1 =3D 4, .crn =3D 10, .crm =3D 3, .opc2 =3D 1, .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, --=20 2.18.0 From nobody Wed Nov 5 10:58:05 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1534251073961596.0921953859674; Tue, 14 Aug 2018 05:51:13 -0700 (PDT) Received: from localhost ([::1]:44205 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fpYmx-0003AQ-AY for importer@patchew.org; Tue, 14 Aug 2018 08:51:07 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43937) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fpYfL-0005ag-VN for qemu-devel@nongnu.org; Tue, 14 Aug 2018 08:43:16 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fpYfL-0002QW-1z for qemu-devel@nongnu.org; Tue, 14 Aug 2018 08:43:15 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:44302) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fpYfI-0001z2-FG; Tue, 14 Aug 2018 08:43:12 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fpYf7-0006nt-5Q; Tue, 14 Aug 2018 13:43:01 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 14 Aug 2018 13:42:46 +0100 Message-Id: <20180814124254.5229-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180814124254.5229-1-peter.maydell@linaro.org> References: <20180814124254.5229-1-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH 02/10] target/arm: Add missing .cp = 15 to HMAIR1 and HAMAIR1 regdefs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgari@xilinx.com, Luc Michel , patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RDMRC_1 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" ARMCPRegInfo structs will not default to .cp =3D 15 if they are ARM_CP_STATE_BOTH, but not if they are ARM_CP_STATE_AA32 (because a coprocessor number of 0 is valid for AArch32). We forgot to explicitly set .cp =3D 15 for the HMAIR1 and HAMAIR1 regdefs, which meant they would UNDEF when the guest tried to access them under cp15. Signed-off-by: Peter Maydell Reviewed-By: Luc Michel Reviewed-by: Edgar E. Iglesias --- A quick grep suggests these are the only ones we got wrong. --- target/arm/helper.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 2c5e02c0b1a..466c8ae492e 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3767,14 +3767,14 @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = =3D { .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, { .name =3D "HMAIR1", .state =3D ARM_CP_STATE_AA32, - .opc1 =3D 4, .crn =3D 10, .crm =3D 2, .opc2 =3D 1, + .cp =3D 15, .opc1 =3D 4, .crn =3D 10, .crm =3D 2, .opc2 =3D 1, .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, { .name =3D "AMAIR_EL2", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 10, .crm =3D 3, .opc2 =3D 0, .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, { .name =3D "HAMAIR1", .state =3D ARM_CP_STATE_AA32, - .opc1 =3D 4, .crn =3D 10, .crm =3D 3, .opc2 =3D 1, + .cp =3D 15, .opc1 =3D 4, .crn =3D 10, .crm =3D 3, .opc2 =3D 1, .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, { .name =3D "AFSR0_EL2", .state =3D ARM_CP_STATE_BOTH, @@ -3917,7 +3917,7 @@ static const ARMCPRegInfo el2_cp_reginfo[] =3D { .access =3D PL2_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.mair= _el[2]), .resetvalue =3D 0 }, { .name =3D "HMAIR1", .state =3D ARM_CP_STATE_AA32, - .opc1 =3D 4, .crn =3D 10, .crm =3D 2, .opc2 =3D 1, + .cp =3D 15, .opc1 =3D 4, .crn =3D 10, .crm =3D 2, .opc2 =3D 1, .access =3D PL2_RW, .type =3D ARM_CP_ALIAS, .fieldoffset =3D offsetofhigh32(CPUARMState, cp15.mair_el[2]) }, { .name =3D "AMAIR_EL2", .state =3D ARM_CP_STATE_BOTH, @@ -3926,7 +3926,7 @@ static const ARMCPRegInfo el2_cp_reginfo[] =3D { .resetvalue =3D 0 }, /* HAMAIR1 is mapped to AMAIR_EL2[63:32] */ { .name =3D "HAMAIR1", .state =3D ARM_CP_STATE_AA32, - .opc1 =3D 4, .crn =3D 10, .crm =3D 3, .opc2 =3D 1, + .cp =3D 15, .opc1 =3D 4, .crn =3D 10, .crm =3D 3, .opc2 =3D 1, .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, { .name =3D "AFSR0_EL2", .state =3D ARM_CP_STATE_BOTH, --=20 2.18.0 From nobody Wed Nov 5 10:58:05 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1534250916977518.5345594314552; Tue, 14 Aug 2018 05:48:36 -0700 (PDT) Received: from localhost ([::1]:44190 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fpYkV-0001Aj-QF for importer@patchew.org; Tue, 14 Aug 2018 08:48:35 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43906) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fpYfL-0005ZR-1M for qemu-devel@nongnu.org; Tue, 14 Aug 2018 08:43:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fpYfK-0002Ot-2g for qemu-devel@nongnu.org; Tue, 14 Aug 2018 08:43:14 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:44334) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fpYfH-0002F2-IW; Tue, 14 Aug 2018 08:43:11 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fpYf8-0006oW-4w; Tue, 14 Aug 2018 13:43:02 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 14 Aug 2018 13:42:47 +0100 Message-Id: <20180814124254.5229-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180814124254.5229-1-peter.maydell@linaro.org> References: <20180814124254.5229-1-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH 03/10] target/arm: Implement RAZ/WI HACTLR2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgari@xilinx.com, Luc Michel , patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RDMRC_1 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The AArch32 HACTLR2 register maps to bits [63:32] of ACTLR_EL2. We implement ACTLR_EL2 as RAZ/WI, so make HACTLR2 also RAZ/WI. (We put the regdef next to ACTLR_EL2 as a reminder in case we ever make ACTLR_EL2 something other than RAZ/WI). Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias --- target/arm/helper.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index 466c8ae492e..14fd78f587a 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5436,6 +5436,11 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 0, .opc2 =3D = 1, .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + /* HACTLR2 maps to ACTLR_EL2[63:32] */ + { .name =3D "HACTLR2", .state =3D ARM_CP_STATE_AA32, + .cp =3D 15, .opc1 =3D 4, .crn =3D 1, .crm =3D 0, .opc2 =3D 3, + .access =3D PL2_RW, .type =3D ARM_CP_CONST, + .resetvalue =3D 0 }, { .name =3D "ACTLR_EL3", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 6, .crn =3D 1, .crm =3D 0, .opc2 =3D = 1, .access =3D PL3_RW, .type =3D ARM_CP_CONST, --=20 2.18.0 From nobody Wed Nov 5 10:58:05 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1534251067420938.7302906973638; Tue, 14 Aug 2018 05:51:07 -0700 (PDT) Received: from localhost ([::1]:44204 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fpYmw-00039K-6o for importer@patchew.org; Tue, 14 Aug 2018 08:51:06 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43852) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fpYfJ-0005XF-FO for qemu-devel@nongnu.org; Tue, 14 Aug 2018 08:43:14 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fpYfI-0002Lg-J1 for qemu-devel@nongnu.org; Tue, 14 Aug 2018 08:43:13 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:44334) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fpYfG-0002F2-JJ; Tue, 14 Aug 2018 08:43:10 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fpYfA-0006pH-Oo; Tue, 14 Aug 2018 13:43:04 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 14 Aug 2018 13:42:48 +0100 Message-Id: <20180814124254.5229-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180814124254.5229-1-peter.maydell@linaro.org> References: <20180814124254.5229-1-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH 04/10] target/arm: Implement AArch32 HVBAR X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgari@xilinx.com, Luc Michel , patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RDMRC_1 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Implement the AArch32 HVBAR register; we can do this just by making the existing VBAR_EL2 regdefs be STATE_BOTH. Signed-off-by: Peter Maydell Reviewed-By: Luc Michel Reviewed-by: Edgar E. Iglesias --- target/arm/helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 14fd78f587a..b6412fe9d1f 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3750,7 +3750,7 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { =20 /* Used to describe the behaviour of EL2 regs when EL2 does not exist. */ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] =3D { - { .name =3D "VBAR_EL2", .state =3D ARM_CP_STATE_AA64, + { .name =3D "VBAR_EL2", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 12, .crm =3D 0, .opc2 =3D 0, .access =3D PL2_RW, .readfn =3D arm_cp_read_zero, .writefn =3D arm_cp_write_ignore }, @@ -3899,7 +3899,7 @@ static const ARMCPRegInfo el2_cp_reginfo[] =3D { .opc0 =3D 3, .opc1 =3D 4, .crn =3D 4, .crm =3D 0, .opc2 =3D 0, .access =3D PL2_RW, .fieldoffset =3D offsetof(CPUARMState, banked_spsr[BANK_HYP]) }, - { .name =3D "VBAR_EL2", .state =3D ARM_CP_STATE_AA64, + { .name =3D "VBAR_EL2", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 12, .crm =3D 0, .opc2 =3D 0, .access =3D PL2_RW, .writefn =3D vbar_write, .fieldoffset =3D offsetof(CPUARMState, cp15.vbar_el[2]), --=20 2.18.0 From nobody Wed Nov 5 10:58:05 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1534250789729939.2271785207012; Tue, 14 Aug 2018 05:46:29 -0700 (PDT) Received: from localhost ([::1]:44175 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fpYiR-0007yB-9R for importer@patchew.org; Tue, 14 Aug 2018 08:46:27 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43892) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fpYfK-0005Yd-Dz for qemu-devel@nongnu.org; Tue, 14 Aug 2018 08:43:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fpYfJ-0002NE-Cb for qemu-devel@nongnu.org; Tue, 14 Aug 2018 08:43:14 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:44302) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fpYfG-0001z2-GB; Tue, 14 Aug 2018 08:43:10 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fpYfB-0006pY-Na; Tue, 14 Aug 2018 13:43:05 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 14 Aug 2018 13:42:49 +0100 Message-Id: <20180814124254.5229-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180814124254.5229-1-peter.maydell@linaro.org> References: <20180814124254.5229-1-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH 05/10] target/arm: Implement AArch32 HCR and HCR2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgari@xilinx.com, Luc Michel , patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RDMRC_1 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The AArch32 HCR and HCR2 registers alias HCR_EL2 bits [31:0] and [63:32]; implement them. Signed-off-by: Peter Maydell Reviewed-by: Edgar E. Iglesias --- target/arm/helper.c | 39 +++++++++++++++++++++++++++++++++++---- 1 file changed, 35 insertions(+), 4 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index b6412fe9d1f..9701e413859 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3754,11 +3754,15 @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = =3D { .opc0 =3D 3, .opc1 =3D 4, .crn =3D 12, .crm =3D 0, .opc2 =3D 0, .access =3D PL2_RW, .readfn =3D arm_cp_read_zero, .writefn =3D arm_cp_write_ignore }, - { .name =3D "HCR_EL2", .state =3D ARM_CP_STATE_AA64, + { .name =3D "HCR_EL2", .state =3D ARM_CP_STATE_BOTH, .type =3D ARM_CP_NO_RAW, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 0, .access =3D PL2_RW, - .readfn =3D arm_cp_read_zero, .writefn =3D arm_cp_write_ignore }, + .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "HCR2", .state =3D ARM_CP_STATE_AA32, + .cp =3D 15, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 4, + .access =3D PL2_RW, + .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, { .name =3D "CPTR_EL2", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 2, .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, @@ -3872,10 +3876,26 @@ static void hcr_write(CPUARMState *env, const ARMCP= RegInfo *ri, uint64_t value) * HCR_PTW forbids certain page-table setups * HCR_DC Disables stage1 and enables stage2 translation */ - if ((raw_read(env, ri) ^ value) & (HCR_VM | HCR_PTW | HCR_DC)) { + if ((env->cp15.hcr_el2 ^ value) & (HCR_VM | HCR_PTW | HCR_DC)) { tlb_flush(CPU(cpu)); } - raw_write(env, ri, value); + env->cp15.hcr_el2 =3D value; +} + +static void hcr_writehigh(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + /* Handle HCR2 write, i.e. write to high half of HCR_EL2 */ + value =3D deposit64(env->cp15.hcr_el2, 32, 32, value); + hcr_write(env, NULL, value); +} + +static void hcr_writelow(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + /* Handle HCR write, i.e. write to low half of HCR_EL2 */ + value =3D deposit64(env->cp15.hcr_el2, 0, 32, value); + hcr_write(env, NULL, value); } =20 static const ARMCPRegInfo el2_cp_reginfo[] =3D { @@ -3883,6 +3903,17 @@ static const ARMCPRegInfo el2_cp_reginfo[] =3D { .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 0, .access =3D PL2_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.hcr_= el2), .writefn =3D hcr_write }, + { .name =3D "HCR", .state =3D ARM_CP_STATE_AA32, + .type =3D ARM_CP_ALIAS, + .cp =3D 15, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 0, + .access =3D PL2_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.hcr_= el2), + .writefn =3D hcr_writelow }, + { .name =3D "HCR2", .state =3D ARM_CP_STATE_AA32, + .type =3D ARM_CP_ALIAS, + .cp =3D 15, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 4, + .access =3D PL2_RW, + .fieldoffset =3D offsetofhigh32(CPUARMState, cp15.hcr_el2), + .writefn =3D hcr_writehigh }, { .name =3D "ELR_EL2", .state =3D ARM_CP_STATE_AA64, .type =3D ARM_CP_ALIAS, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 4, .crm =3D 0, .opc2 =3D 1, --=20 2.18.0 From nobody Wed Nov 5 10:58:05 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1534250892925978.1882830721332; Tue, 14 Aug 2018 05:48:12 -0700 (PDT) Received: from localhost ([::1]:44188 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fpYk7-0000zE-T1 for importer@patchew.org; Tue, 14 Aug 2018 08:48:11 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43785) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fpYfH-0005VO-UN for qemu-devel@nongnu.org; Tue, 14 Aug 2018 08:43:13 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fpYfG-0002IO-SB for qemu-devel@nongnu.org; Tue, 14 Aug 2018 08:43:11 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:44302) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fpYfE-0001z2-I0; Tue, 14 Aug 2018 08:43:08 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fpYfC-0006q5-M7; Tue, 14 Aug 2018 13:43:06 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 14 Aug 2018 13:42:50 +0100 Message-Id: <20180814124254.5229-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180814124254.5229-1-peter.maydell@linaro.org> References: <20180814124254.5229-1-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH 06/10] target/arm: Implement AArch32 Hyp FARs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgari@xilinx.com, Luc Michel , patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RDMRC_1 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The AArch32 virtualization extensions support these fault address registers: * HDFAR: aliased with AArch64 FAR_EL2[31:0] and AArch32 DFAR(S) * HIFAR: aliased with AArch64 FAR_EL2[63:32] and AArch32 IFAR(S) Implement the accessors for these. This fixes in passing a bug where we weren't implementing the "RES0 from EL3 if EL2 not implemented" behaviour for AArch64 FAR_EL2. Signed-off-by: Peter Maydell Reviewed-By: Luc Michel Reviewed-by: Edgar E. Iglesias --- target/arm/helper.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 9701e413859..d6e98e9d606 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3847,6 +3847,13 @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = =3D { { .name =3D "HSTR_EL2", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 3, .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "FAR_EL2", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 6, .crm =3D 0, .opc2 =3D 0, + .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "HIFAR", .state =3D ARM_CP_STATE_AA32, + .type =3D ARM_CP_CONST, + .cp =3D 15, .opc1 =3D 4, .crn =3D 6, .crm =3D 0, .opc2 =3D 2, + .access =3D PL2_RW, .resetvalue =3D 0 }, REGINFO_SENTINEL }; =20 @@ -3922,9 +3929,14 @@ static const ARMCPRegInfo el2_cp_reginfo[] =3D { { .name =3D "ESR_EL2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 5, .crm =3D 2, .opc2 =3D 0, .access =3D PL2_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.esr_= el[2]) }, - { .name =3D "FAR_EL2", .state =3D ARM_CP_STATE_AA64, + { .name =3D "FAR_EL2", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 6, .crm =3D 0, .opc2 =3D 0, .access =3D PL2_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.far_= el[2]) }, + { .name =3D "HIFAR", .state =3D ARM_CP_STATE_AA32, + .type =3D ARM_CP_ALIAS, + .cp =3D 15, .opc1 =3D 4, .crn =3D 6, .crm =3D 0, .opc2 =3D 2, + .access =3D PL2_RW, + .fieldoffset =3D offsetofhigh32(CPUARMState, cp15.far_el[2]) }, { .name =3D "SPSR_EL2", .state =3D ARM_CP_STATE_AA64, .type =3D ARM_CP_ALIAS, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 4, .crm =3D 0, .opc2 =3D 0, --=20 2.18.0 From nobody Wed Nov 5 10:58:05 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1534250722336180.74793065698464; Tue, 14 Aug 2018 05:45:22 -0700 (PDT) Received: from localhost ([::1]:44167 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fpYhH-00070c-Pj for importer@patchew.org; Tue, 14 Aug 2018 08:45:15 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43809) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fpYfI-0005W6-Jh for qemu-devel@nongnu.org; Tue, 14 Aug 2018 08:43:13 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fpYfH-0002Jg-KL for qemu-devel@nongnu.org; Tue, 14 Aug 2018 08:43:12 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:44302) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fpYfF-0001z2-Gx; Tue, 14 Aug 2018 08:43:09 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fpYfD-0006qa-Jg; Tue, 14 Aug 2018 13:43:07 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 14 Aug 2018 13:42:51 +0100 Message-Id: <20180814124254.5229-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180814124254.5229-1-peter.maydell@linaro.org> References: <20180814124254.5229-1-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH 07/10] target/arm: Implement ESR_EL2/HSR for AArch32 and no-EL2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgari@xilinx.com, Luc Michel , patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RDMRC_1 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The AArch32 HSR is the equivalent of AArch64 ESR_EL2; we can implement it by marking our existing ESR_EL2 regdef as STATE_BOTH. It also needs to be "RES0 from EL3 if EL2 not implemented", so add the missing stanza to el3_no_el2_cp_reginfo. Signed-off-by: Peter Maydell Reviewed-By: Luc Michel Reviewed-by: Edgar E. Iglesias --- target/arm/helper.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index d6e98e9d606..80855302089 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3763,6 +3763,10 @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = =3D { .cp =3D 15, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 4, .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "ESR_EL2", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 5, .crm =3D 2, .opc2 =3D 0, + .access =3D PL2_RW, + .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, { .name =3D "CPTR_EL2", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 2, .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, @@ -3926,7 +3930,7 @@ static const ARMCPRegInfo el2_cp_reginfo[] =3D { .opc0 =3D 3, .opc1 =3D 4, .crn =3D 4, .crm =3D 0, .opc2 =3D 1, .access =3D PL2_RW, .fieldoffset =3D offsetof(CPUARMState, elr_el[2]) }, - { .name =3D "ESR_EL2", .state =3D ARM_CP_STATE_AA64, + { .name =3D "ESR_EL2", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 5, .crm =3D 2, .opc2 =3D 0, .access =3D PL2_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.esr_= el[2]) }, { .name =3D "FAR_EL2", .state =3D ARM_CP_STATE_BOTH, --=20 2.18.0 From nobody Wed Nov 5 10:58:05 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1534250743734993.9935290121191; Tue, 14 Aug 2018 05:45:43 -0700 (PDT) Received: from localhost ([::1]:44170 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fpYhc-0007Gi-KE for importer@patchew.org; Tue, 14 Aug 2018 08:45:36 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43857) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fpYfJ-0005XT-Go for qemu-devel@nongnu.org; Tue, 14 Aug 2018 08:43:14 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fpYfI-0002L9-84 for qemu-devel@nongnu.org; Tue, 14 Aug 2018 08:43:13 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:44334) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fpYfF-0002F2-KJ; Tue, 14 Aug 2018 08:43:09 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fpYfE-0006r7-Hd; Tue, 14 Aug 2018 13:43:08 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 14 Aug 2018 13:42:52 +0100 Message-Id: <20180814124254.5229-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180814124254.5229-1-peter.maydell@linaro.org> References: <20180814124254.5229-1-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH 08/10] target/arm: Permit accesses to ELR_Hyp from Hyp mode via MSR/MRS (banked) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgari@xilinx.com, Luc Michel , patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RDMRC_1 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The MSR (banked) and MRS (banked) instructions allow accesses to ELR_Hyp from either Monitor or Hyp mode. Our translate time check was overly strict and only permitted access from Monitor mode. The runtime check wo do in msr_mrs_banked_exc_checks() had the correct code in it, but never got there because of the earlier "currmode =3D=3D tgtmode" check. Special case ELR_Hyp. Signed-off-by: Peter Maydell Reviewed-By: Luc Michel Reviewed-by: Edgar E. Iglesias --- target/arm/op_helper.c | 22 +++++++++++----------- target/arm/translate.c | 10 +++++++--- 2 files changed, 18 insertions(+), 14 deletions(-) diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index d550978b5b9..952b8d122b7 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -611,6 +611,14 @@ static void msr_mrs_banked_exc_checks(CPUARMState *env= , uint32_t tgtmode, */ int curmode =3D env->uncached_cpsr & CPSR_M; =20 + if (regno =3D=3D 17) { + /* ELR_Hyp: a special case because access from tgtmode is OK */ + if (curmode !=3D ARM_CPU_MODE_HYP && curmode !=3D ARM_CPU_MODE_MON= ) { + goto undef; + } + return; + } + if (curmode =3D=3D tgtmode) { goto undef; } @@ -638,17 +646,9 @@ static void msr_mrs_banked_exc_checks(CPUARMState *env= , uint32_t tgtmode, } =20 if (tgtmode =3D=3D ARM_CPU_MODE_HYP) { - switch (regno) { - case 17: /* ELR_Hyp */ - if (curmode !=3D ARM_CPU_MODE_HYP && curmode !=3D ARM_CPU_MODE= _MON) { - goto undef; - } - break; - default: - if (curmode !=3D ARM_CPU_MODE_MON) { - goto undef; - } - break; + /* SPSR_Hyp, r13_hyp: accessible from Monitor mode only */ + if (curmode !=3D ARM_CPU_MODE_MON) { + goto undef; } } =20 diff --git a/target/arm/translate.c b/target/arm/translate.c index f845da7c638..3f5751d4826 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -4506,10 +4506,14 @@ static bool msr_banked_access_decode(DisasContext *= s, int r, int sysm, int rn, } break; case ARM_CPU_MODE_HYP: - /* Note that we can forbid accesses from EL2 here because they - * must be from Hyp mode itself + /* + * SPSR_hyp and r13_hyp can only be accessed from Monitor mode + * (and so we can forbid accesses from EL2 or below). elr_hyp + * can be accessed also from Hyp mode, so forbid accesses from + * EL0 or EL1. */ - if (!arm_dc_feature(s, ARM_FEATURE_EL2) || s->current_el < 3) { + if (!arm_dc_feature(s, ARM_FEATURE_EL2) || s->current_el < 2 || + (s->current_el < 3 && *regno !=3D 17)) { goto undef; } break; --=20 2.18.0 From nobody Wed Nov 5 10:58:05 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1534250913371183.43389851750862; Tue, 14 Aug 2018 05:48:33 -0700 (PDT) Received: from localhost ([::1]:44189 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fpYkS-00017U-76 for importer@patchew.org; Tue, 14 Aug 2018 08:48:32 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43905) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fpYfK-0005ZP-UV for qemu-devel@nongnu.org; Tue, 14 Aug 2018 08:43:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fpYfK-0002P0-4s for qemu-devel@nongnu.org; Tue, 14 Aug 2018 08:43:14 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:44302) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fpYfH-0001z2-Fm; Tue, 14 Aug 2018 08:43:11 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fpYfF-0006rR-Fk; Tue, 14 Aug 2018 13:43:09 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 14 Aug 2018 13:42:53 +0100 Message-Id: <20180814124254.5229-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180814124254.5229-1-peter.maydell@linaro.org> References: <20180814124254.5229-1-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH 09/10] target/arm: Implement AArch32 ERET instruction X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgari@xilinx.com, Luc Michel , patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RDMRC_1 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" ARMv7VE introduced the ERET instruction, which is necessary to return from an exception taken to Hyp mode. Implement this. In A32 encoding it is a completely new encoding; in T32 it is an adjustment of the behaviour of the existing "SUBS PC, LR, #" instruction. Signed-off-by: Peter Maydell Reviewed-By: Luc Michel Reviewed-by: Edgar E. Iglesias --- target/arm/translate.c | 31 +++++++++++++++++++++++++++++-- 1 file changed, 29 insertions(+), 2 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 3f5751d4826..5ecc24f12fb 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8887,6 +8887,25 @@ static void disas_arm_insn(DisasContext *s, unsigned= int insn) tcg_temp_free_i32(tmp2); store_reg(s, rd, tmp); break; + case 0x6: /* ERET */ + if (op1 !=3D 3) { + goto illegal_op; + } + if (!arm_dc_feature(s, ARM_FEATURE_V7VE)) { + goto illegal_op; + } + if ((insn & 0x000fff0f) !=3D 0x0000000e) { + /* UNPREDICTABLE; we choose to UNDEF */ + goto illegal_op; + } + + if (s->current_el =3D=3D 2) { + tmp =3D load_cpu_field(elr_el[2]); + } else { + tmp =3D load_reg(s, 14); + } + gen_exception_return(s, tmp); + break; case 7: { int imm16 =3D extract32(insn, 0, 4) | (extract32(insn, 8, 12) = << 4); @@ -11144,8 +11163,16 @@ static void disas_thumb2_insn(DisasContext *s, uin= t32_t insn) if (rn !=3D 14 || rd !=3D 15) { goto illegal_op; } - tmp =3D load_reg(s, rn); - tcg_gen_subi_i32(tmp, tmp, insn & 0xff); + if (s->current_el =3D=3D 2) { + /* ERET from Hyp uses ELR_Hyp, not LR */ + if (insn & 0xff) { + goto illegal_op; + } + tmp =3D load_cpu_field(elr_el[2]); + } else { + tmp =3D load_reg(s, rn); + tcg_gen_subi_i32(tmp, tmp, insn & 0xff); + } gen_exception_return(s, tmp); break; case 6: /* MRS */ --=20 2.18.0 From nobody Wed Nov 5 10:58:05 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1534251222429759.8889651306845; Tue, 14 Aug 2018 05:53:42 -0700 (PDT) Received: from localhost ([::1]:44215 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fpYpR-0005yo-8A for importer@patchew.org; Tue, 14 Aug 2018 08:53:41 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43942) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fpYfM-0005b9-8n for qemu-devel@nongnu.org; Tue, 14 Aug 2018 08:43:17 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fpYfL-0002Qj-2q for qemu-devel@nongnu.org; Tue, 14 Aug 2018 08:43:16 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:44346) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fpYfH-0002IZ-GC; Tue, 14 Aug 2018 08:43:11 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fpYfG-0006sF-Dd; Tue, 14 Aug 2018 13:43:10 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 14 Aug 2018 13:42:54 +0100 Message-Id: <20180814124254.5229-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180814124254.5229-1-peter.maydell@linaro.org> References: <20180814124254.5229-1-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH 10/10] target/arm: Implement support for taking exceptions to Hyp mode X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgari@xilinx.com, Luc Michel , patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RDMRC_1 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Implement the necessary support code for taking exceptions to Hyp mode in AArch32. Signed-off-by: Peter Maydell --- target/arm/helper.c | 146 +++++++++++++++++++++++++++++++++++++------- 1 file changed, 123 insertions(+), 23 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 80855302089..167203ac664 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8013,6 +8013,123 @@ void aarch64_sync_64_to_32(CPUARMState *env) env->regs[15] =3D env->pc; } =20 +static void take_aarch32_exception(CPUARMState *env, int new_mode, + uint32_t mask, uint32_t offset, + uint32_t newpc) +{ + /* Change the CPU state so as to actually take the exception. */ + switch_mode(env, new_mode); + /* + * For exceptions taken to AArch32 we must clear the SS bit in both + * PSTATE and in the old-state value we save to SPSR_, so zero i= t now. + */ + env->uncached_cpsr &=3D ~PSTATE_SS; + env->spsr =3D cpsr_read(env); + /* Clear IT bits. */ + env->condexec_bits =3D 0; + /* Switch to the new mode, and to the correct instruction set. */ + env->uncached_cpsr =3D (env->uncached_cpsr & ~CPSR_M) | new_mode; + /* Set new mode endianness */ + env->uncached_cpsr &=3D ~CPSR_E; + if (env->cp15.sctlr_el[arm_current_el(env)] & SCTLR_EE) { + env->uncached_cpsr |=3D CPSR_E; + } + env->daif |=3D mask; + + if (new_mode =3D=3D ARM_CPU_MODE_HYP) { + env->thumb =3D (env->cp15.sctlr_el[2] & SCTLR_TE) !=3D 0; + env->elr_el[2] =3D env->regs[15]; + } else { + /* + * this is a lie, as there was no c1_sys on V4T/V5, but who cares + * and we should just guard the thumb mode on V4 + */ + if (arm_feature(env, ARM_FEATURE_V4T)) { + env->thumb =3D + (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_TE) !=3D 0; + } + env->regs[14] =3D env->regs[15] + offset; + } + env->regs[15] =3D newpc; +} + +static void arm_cpu_do_interrupt_aarch32_hyp(CPUState *cs) +{ + /* + * Handle exception entry to Hyp mode; this is sufficiently + * different to entry to other AArch32 modes that we handle it + * separately here. + * + * The vector table entry used is always the 0x14 Hyp mode entry point, + * unless this is an UNDEF/HVC/abort taken from Hyp to Hyp. + * The offset applied to the preferred return address is always zero + * (see DDI0487C.a section G1.12.3). + * PSTATE A/I/F masks are set based only on the SCR.EA/IRQ/FIQ values. + */ + uint32_t addr, mask; + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + + switch (cs->exception_index) { + case EXCP_UDEF: + addr =3D 0x04; + break; + case EXCP_SWI: + addr =3D 0x14; + break; + case EXCP_BKPT: + /* Fall through to prefetch abort. */ + case EXCP_PREFETCH_ABORT: + env->cp15.ifar_s =3D env->exception.vaddress; + qemu_log_mask(CPU_LOG_INT, "...with HIFAR 0x%x\n", + (uint32_t)env->exception.vaddress); + addr =3D 0x0c; + break; + case EXCP_DATA_ABORT: + env->cp15.dfar_s =3D env->exception.vaddress; + qemu_log_mask(CPU_LOG_INT, "...with HDFAR 0x%x\n", + (uint32_t)env->exception.vaddress); + addr =3D 0x10; + break; + case EXCP_IRQ: + addr =3D 0x18; + break; + case EXCP_FIQ: + addr =3D 0x1c; + break; + case EXCP_HVC: + addr =3D 0x08; + break; + case EXCP_HYP_TRAP: + addr =3D 0x14; + default: + cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); + } + + if (cs->exception_index !=3D EXCP_IRQ && cs->exception_index !=3D EXCP= _FIQ) { + env->cp15.esr_el[2] =3D env->exception.syndrome; + } + + if (arm_current_el(env) !=3D 2 && addr < 0x14) { + addr =3D 0x14; + } + + mask =3D 0; + if (!(env->cp15.scr_el3 & SCR_EA)) { + mask |=3D CPSR_A; + } + if (!(env->cp15.scr_el3 & SCR_IRQ)) { + mask |=3D CPSR_I; + } + if (!(env->cp15.scr_el3 & SCR_IRQ)) { + mask |=3D CPSR_F; + } + + addr +=3D env->cp15.hvbar; + + take_aarch32_exception(env, ARM_CPU_MODE_HYP, mask, 0, addr); +} + static void arm_cpu_do_interrupt_aarch32(CPUState *cs) { ARMCPU *cpu =3D ARM_CPU(cs); @@ -8048,6 +8165,11 @@ static void arm_cpu_do_interrupt_aarch32(CPUState *c= s) env->cp15.mdscr_el1 =3D deposit64(env->cp15.mdscr_el1, 2, 4, moe); } =20 + if (env->exception.target_el =3D=3D 2) { + arm_cpu_do_interrupt_aarch32_hyp(cs); + return; + } + /* TODO: Vectored interrupt controller. */ switch (cs->exception_index) { case EXCP_UDEF: @@ -8155,29 +8277,7 @@ static void arm_cpu_do_interrupt_aarch32(CPUState *c= s) env->cp15.scr_el3 &=3D ~SCR_NS; } =20 - switch_mode (env, new_mode); - /* For exceptions taken to AArch32 we must clear the SS bit in both - * PSTATE and in the old-state value we save to SPSR_, so zero i= t now. - */ - env->uncached_cpsr &=3D ~PSTATE_SS; - env->spsr =3D cpsr_read(env); - /* Clear IT bits. */ - env->condexec_bits =3D 0; - /* Switch to the new mode, and to the correct instruction set. */ - env->uncached_cpsr =3D (env->uncached_cpsr & ~CPSR_M) | new_mode; - /* Set new mode endianness */ - env->uncached_cpsr &=3D ~CPSR_E; - if (env->cp15.sctlr_el[arm_current_el(env)] & SCTLR_EE) { - env->uncached_cpsr |=3D CPSR_E; - } - env->daif |=3D mask; - /* this is a lie, as the was no c1_sys on V4T/V5, but who cares - * and we should just guard the thumb mode on V4 */ - if (arm_feature(env, ARM_FEATURE_V4T)) { - env->thumb =3D (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_TE)= !=3D 0; - } - env->regs[14] =3D env->regs[15] + offset; - env->regs[15] =3D addr; + take_aarch32_exception(env, new_mode, mask, offset, addr); } =20 /* Handle exception entry to a target EL which is using AArch64 */ --=20 2.18.0