From nobody Tue Feb 10 10:07:55 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1533978830815512.93119901251; Sat, 11 Aug 2018 02:13:50 -0700 (PDT) Received: from localhost ([::1]:59389 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1foPy1-0001rj-HY for importer@patchew.org; Sat, 11 Aug 2018 05:13:49 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55082) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1foPtD-0005to-9Q for qemu-devel@nongnu.org; Sat, 11 Aug 2018 05:08:52 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1foPtB-0001IV-TB for qemu-devel@nongnu.org; Sat, 11 Aug 2018 05:08:51 -0400 Received: from steffen-goertz.de ([88.198.119.201]:34686) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1foPt8-0001BC-9l; Sat, 11 Aug 2018 05:08:46 -0400 Received: from localhost.localdomain (tmo-080-6.customers.d1-online.com [80.187.80.6]) by steffen-goertz.de (Postfix) with ESMTPSA id B4BB94BBB1; Sat, 11 Aug 2018 11:05:37 +0200 (CEST) From: =?UTF-8?q?Steffen=20G=C3=B6rtz?= To: qemu-devel@nongnu.org Date: Sat, 11 Aug 2018 11:08:32 +0200 Message-Id: <20180811090836.4024-4-contrib@steffen-goertz.de> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180811090836.4024-1-contrib@steffen-goertz.de> References: <20180811090836.4024-1-contrib@steffen-goertz.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 88.198.119.201 Subject: [Qemu-devel] [PATCH 3/7] arm: Add chip variant property to nRF51 SoC X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Jim Mussared , Stefan Hajnoczi , =?UTF-8?q?Steffen=20G=C3=B6rtz?= , qemu-arm@nongnu.org, Joel Stanley , Julia Suvorova Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Nordic Semiconductor nRF51 SOCs are available in different "variants" which differ in available memory. This patchs adds a "variant" attribute to the SOC so that the user can choose between different variants and thus memory sizes. See product specification http://infocenter.nordicsemi.com/pdf/nRF51822_PS_= v3.1.pdf section 10.6 Signed-off-by: Steffen G=C3=B6rtz --- hw/arm/microbit.c | 4 ++-- hw/arm/nrf51_soc.c | 40 +++++++++++++++++++++++++++----------- include/hw/arm/nrf51_soc.h | 15 +++++++++++--- 3 files changed, 43 insertions(+), 16 deletions(-) diff --git a/hw/arm/microbit.c b/hw/arm/microbit.c index 8f3c446f52..d6776dea0a 100644 --- a/hw/arm/microbit.c +++ b/hw/arm/microbit.c @@ -27,11 +27,11 @@ static void microbit_init(MachineState *machine) object_property_add_child(OBJECT(machine), "nrf51", soc, &error_fatal); object_property_set_link(soc, OBJECT(system_memory), "memory", &error_abort); + qdev_prop_set_uint32(DEVICE(soc), "variant", NRF51_VARIANT_AA); =20 object_property_set_bool(soc, true, "realized", &error_abort); =20 - armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, - NRF51_SOC(soc)->flash_size); + armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, 0x00); } =20 =20 diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c index 441d05e1ef..85bce2c1e0 100644 --- a/hw/arm/nrf51_soc.c +++ b/hw/arm/nrf51_soc.c @@ -32,15 +32,21 @@ #define FLASH_BASE 0x00000000 #define SRAM_BASE 0x20000000 =20 -/* The size and base is for the NRF51822 part. If other parts - * are supported in the future, add a sub-class of NRF51SoC for - * the specific variants */ -#define NRF51822_FLASH_SIZE (256 * 1024) -#define NRF51822_SRAM_SIZE (16 * 1024) +#define PAGE_SIZE 1024 =20 /* IRQ lines can be derived from peripheral base addresses */ #define BASE_TO_IRQ(base) (((base) >> 12) & 0x1F) =20 +/* RAM and CODE size in number of pages for different NRF51Variants varian= ts */ +struct { + hwaddr ram_size; + hwaddr flash_size; +} NRF51VariantAttributes[] =3D { + [NRF51_VARIANT_AA] =3D {.ram_size =3D 16, .flash_size =3D 256 }, + [NRF51_VARIANT_AB] =3D {.ram_size =3D 16, .flash_size =3D 128 }, + [NRF51_VARIANT_AC] =3D {.ram_size =3D 32, .flash_size =3D 256 }, +}; + static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp) { NRF51State *s =3D NRF51_SOC(dev_soc); @@ -51,13 +57,21 @@ static void nrf51_soc_realize(DeviceState *dev_soc, Err= or **errp) return; } =20 + if (!(s->part_variant > NRF51_VARIANT_INVALID + && s->part_variant < NRF51_VARIANT_MAX)) { + error_setg(errp, "VARIANT not set or invalid"); + return; + } + object_property_set_link(OBJECT(&s->cpu), OBJECT(&s->container), "memo= ry", &err); object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err); =20 memory_region_add_subregion_overlap(&s->container, 0, s->board_memory,= -1); =20 - memory_region_init_ram(&s->flash, OBJECT(s), "nrf51.flash", s->flash_s= ize, + /* FLASH */ + memory_region_init_ram(&s->flash, NULL, "nrf51_soc.flash", + NRF51VariantAttributes[s->part_variant].flash_size * PAGE_SIZE, &err); if (err) { error_propagate(errp, err); @@ -66,7 +80,9 @@ static void nrf51_soc_realize(DeviceState *dev_soc, Error= **errp) memory_region_set_readonly(&s->flash, true); memory_region_add_subregion(&s->container, FLASH_BASE, &s->flash); =20 - memory_region_init_ram(&s->sram, NULL, "nrf51.sram", s->sram_size, &er= r); + /* SRAM */ + memory_region_init_ram(&s->sram, NULL, "nrf51_soc.sram", + NRF51VariantAttributes[s->part_variant].ram_size * PAGE_SIZE, = &err); if (err) { error_propagate(errp, err); return; @@ -85,17 +101,19 @@ static void nrf51_soc_init(Object *obj) memory_region_init(&s->container, obj, "nrf51-container", UINT64_MAX); =20 object_initialize(&s->cpu, sizeof(s->cpu), TYPE_ARMV7M); - object_property_add_child(OBJECT(s), "armv6m", OBJECT(&s->cpu), &error= _abort); + object_property_add_child(OBJECT(s), "armv6m", OBJECT(&s->cpu), + &error_abort); qdev_set_parent_bus(DEVICE(&s->cpu), sysbus_get_default()); - qdev_prop_set_string(DEVICE(&s->cpu), "cpu-type", ARM_CPU_TYPE_NAME("c= ortex-m0")); + qdev_prop_set_string(DEVICE(&s->cpu), "cpu-type", + ARM_CPU_TYPE_NAME("cortex-m0")); qdev_prop_set_uint32(DEVICE(&s->cpu), "num-irq", 32); } =20 static Property nrf51_soc_properties[] =3D { DEFINE_PROP_LINK("memory", NRF51State, board_memory, TYPE_MEMORY_REGIO= N, MemoryRegion *), - DEFINE_PROP_UINT32("sram-size", NRF51State, sram_size, NRF51822_SRAM_S= IZE), - DEFINE_PROP_UINT32("flash-size", NRF51State, flash_size, NRF51822_FLAS= H_SIZE), + DEFINE_PROP_INT32("variant", NRF51State, part_variant, + NRF51_VARIANT_INVALID), DEFINE_PROP_END_OF_LIST(), }; =20 diff --git a/include/hw/arm/nrf51_soc.h b/include/hw/arm/nrf51_soc.h index e380ec26b8..24212f9174 100644 --- a/include/hw/arm/nrf51_soc.h +++ b/include/hw/arm/nrf51_soc.h @@ -29,14 +29,23 @@ typedef struct NRF51State { MemoryRegion sram; MemoryRegion flash; =20 - uint32_t sram_size; - uint32_t flash_size; - MemoryRegion *board_memory; =20 MemoryRegion container; =20 + /* Properties */ + int32_t part_variant; } NRF51State; =20 + +/* Variants as described in nRF51 product specification section 10.6 table= 73 */ +typedef enum { + NRF51_VARIANT_INVALID =3D -1, + NRF51_VARIANT_AA =3D 0, + NRF51_VARIANT_AB =3D 1, + NRF51_VARIANT_AC =3D 2, + NRF51_VARIANT_MAX =3D 3 +} NRF51Variants; + #endif =20 --=20 2.18.0