From nobody Tue May 7 22:50:33 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1533978844081340.29860670168466; Sat, 11 Aug 2018 02:14:04 -0700 (PDT) Received: from localhost ([::1]:59391 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1foPyE-00022k-UG for importer@patchew.org; Sat, 11 Aug 2018 05:14:02 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55138) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1foPtF-0005vv-DY for qemu-devel@nongnu.org; Sat, 11 Aug 2018 05:08:54 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1foPtE-0001MW-CT for qemu-devel@nongnu.org; Sat, 11 Aug 2018 05:08:53 -0400 Received: from steffen-goertz.de ([88.198.119.201]:34660) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1foPt6-00015R-Be; Sat, 11 Aug 2018 05:08:44 -0400 Received: from localhost.localdomain (tmo-080-6.customers.d1-online.com [80.187.80.6]) by steffen-goertz.de (Postfix) with ESMTPSA id 0008F4BBA2; Sat, 11 Aug 2018 11:05:34 +0200 (CEST) From: =?UTF-8?q?Steffen=20G=C3=B6rtz?= To: qemu-devel@nongnu.org Date: Sat, 11 Aug 2018 11:08:30 +0200 Message-Id: <20180811090836.4024-2-contrib@steffen-goertz.de> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180811090836.4024-1-contrib@steffen-goertz.de> References: <20180811090836.4024-1-contrib@steffen-goertz.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 88.198.119.201 Subject: [Qemu-devel] [PATCH 1/7] hw/arm/nrf51_soc: nRF51 Calculate peripheral id from base address X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Jim Mussared , Stefan Hajnoczi , =?UTF-8?q?Steffen=20G=C3=B6rtz?= , qemu-arm@nongnu.org, Joel Stanley , Julia Suvorova Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" The base address determines a peripherals id, which identifies its interrupt line, see NRF51 reference manual section 10 peripheral interface. This little gem calculates the peripheral id based on its base address. Signed-off-by: Steffen G=C3=B6rtz Reviewed-by: Peter Maydell --- hw/arm/nrf51_soc.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c index 9f9649c780..441d05e1ef 100644 --- a/hw/arm/nrf51_soc.c +++ b/hw/arm/nrf51_soc.c @@ -38,6 +38,9 @@ #define NRF51822_FLASH_SIZE (256 * 1024) #define NRF51822_SRAM_SIZE (16 * 1024) =20 +/* IRQ lines can be derived from peripheral base addresses */ +#define BASE_TO_IRQ(base) (((base) >> 12) & 0x1F) + static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp) { NRF51State *s =3D NRF51_SOC(dev_soc); --=20 2.18.0 From nobody Tue May 7 22:50:33 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 15339786727121005.1499548274759; Sat, 11 Aug 2018 02:11:12 -0700 (PDT) Received: from localhost ([::1]:59376 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1foPvH-0007zC-1N for importer@patchew.org; Sat, 11 Aug 2018 05:10:59 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55074) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1foPtC-0005tX-UW for qemu-devel@nongnu.org; Sat, 11 Aug 2018 05:08:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1foPtB-0001IF-Qe for qemu-devel@nongnu.org; Sat, 11 Aug 2018 05:08:50 -0400 Received: from steffen-goertz.de ([88.198.119.201]:34678) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1foPt7-00018M-55; Sat, 11 Aug 2018 05:08:45 -0400 Received: from localhost.localdomain (tmo-080-6.customers.d1-online.com [80.187.80.6]) by steffen-goertz.de (Postfix) with ESMTPSA id 913604BBB0; Sat, 11 Aug 2018 11:05:36 +0200 (CEST) From: =?UTF-8?q?Steffen=20G=C3=B6rtz?= To: qemu-devel@nongnu.org Date: Sat, 11 Aug 2018 11:08:31 +0200 Message-Id: <20180811090836.4024-3-contrib@steffen-goertz.de> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180811090836.4024-1-contrib@steffen-goertz.de> References: <20180811090836.4024-1-contrib@steffen-goertz.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 88.198.119.201 Subject: [Qemu-devel] [PATCH 2/7] arm: Move nRF51 machine state to dedicated header X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Jim Mussared , Stefan Hajnoczi , =?UTF-8?q?Steffen=20G=C3=B6rtz?= , qemu-arm@nongnu.org, Joel Stanley , Julia Suvorova Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" The machine state will be used to host the SOC and board level devices like the LED matrix and devices to handle to pushbuttons A and B. Signed-off-by: Steffen G=C3=B6rtz --- hw/arm/microbit.c | 38 ++++++++++++++++++++++++-------------- include/hw/arm/microbit.h | 29 +++++++++++++++++++++++++++++ 2 files changed, 53 insertions(+), 14 deletions(-) create mode 100644 include/hw/arm/microbit.h diff --git a/hw/arm/microbit.c b/hw/arm/microbit.c index 467cfbda23..8f3c446f52 100644 --- a/hw/arm/microbit.c +++ b/hw/arm/microbit.c @@ -14,22 +14,11 @@ #include "hw/arm/arm.h" #include "exec/address-spaces.h" =20 -#include "hw/arm/nrf51_soc.h" - -typedef struct { - MachineState parent; - - NRF51State nrf51; -} MICROBITMachineState; - -#define TYPE_MICROBIT_MACHINE "microbit" - -#define MICROBIT_MACHINE(obj) \ - OBJECT_CHECK(MICROBITMachineState, obj, TYPE_MICROBIT_MACHINE) +#include "hw/arm/microbit.h" =20 static void microbit_init(MachineState *machine) { - MICROBITMachineState *s =3D g_new(MICROBITMachineState, 1); + MicrobitMachineState *s =3D MICROBIT_MACHINE(machine); MemoryRegion *system_memory =3D get_system_memory(); Object *soc; =20 @@ -45,10 +34,31 @@ static void microbit_init(MachineState *machine) NRF51_SOC(soc)->flash_size); } =20 + static void microbit_machine_init(MachineClass *mc) { mc->desc =3D "BBC micro:bit"; mc->init =3D microbit_init; mc->max_cpus =3D 1; } -DEFINE_MACHINE("microbit", microbit_machine_init); + +static void microbit_machine_init_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc =3D MACHINE_CLASS(oc); + microbit_machine_init(mc); +} + +static const TypeInfo microbit_machine_info =3D { + .name =3D TYPE_MICROBIT_MACHINE, + .parent =3D TYPE_MACHINE, + .instance_size =3D sizeof(MicrobitMachineState), + .class_init =3D microbit_machine_init_class_init, +}; + +static void microbit_machine_types(void) +{ + type_register_static(µbit_machine_info); +} + +type_init(microbit_machine_types) + diff --git a/include/hw/arm/microbit.h b/include/hw/arm/microbit.h new file mode 100644 index 0000000000..89f0c6bc07 --- /dev/null +++ b/include/hw/arm/microbit.h @@ -0,0 +1,29 @@ +/* + * BBC micro:bit machine + * + * Copyright 2018 Joel Stanley + * Copyright 2018 Steffen G=C3=B6rtz + * + * This code is licensed under the GPL version 2 or later. See + * the COPYING file in the top-level directory. + */ +#ifndef MICROBIT_H +#define MICROBIT_H + +#include "qemu/osdep.h" +#include "hw/qdev-core.h" +#include "hw/arm/nrf51_soc.h" +#include "hw/display/led_matrix.h" + +#define TYPE_MICROBIT_MACHINE MACHINE_TYPE_NAME("microbit") +#define MICROBIT_MACHINE(obj) \ + OBJECT_CHECK(MicrobitMachineState, (obj), TYPE_MICROBIT_MACHINE) + +typedef struct MicrobitMachineState { + /*< private >*/ + MachineState parent_obj; + + NRF51State nrf51; +} MicrobitMachineState; + +#endif --=20 2.18.0 From nobody Tue May 7 22:50:33 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1533978830815512.93119901251; Sat, 11 Aug 2018 02:13:50 -0700 (PDT) Received: from localhost ([::1]:59389 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1foPy1-0001rj-HY for importer@patchew.org; Sat, 11 Aug 2018 05:13:49 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55082) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1foPtD-0005to-9Q for qemu-devel@nongnu.org; Sat, 11 Aug 2018 05:08:52 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1foPtB-0001IV-TB for qemu-devel@nongnu.org; Sat, 11 Aug 2018 05:08:51 -0400 Received: from steffen-goertz.de ([88.198.119.201]:34686) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1foPt8-0001BC-9l; Sat, 11 Aug 2018 05:08:46 -0400 Received: from localhost.localdomain (tmo-080-6.customers.d1-online.com [80.187.80.6]) by steffen-goertz.de (Postfix) with ESMTPSA id B4BB94BBB1; Sat, 11 Aug 2018 11:05:37 +0200 (CEST) From: =?UTF-8?q?Steffen=20G=C3=B6rtz?= To: qemu-devel@nongnu.org Date: Sat, 11 Aug 2018 11:08:32 +0200 Message-Id: <20180811090836.4024-4-contrib@steffen-goertz.de> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180811090836.4024-1-contrib@steffen-goertz.de> References: <20180811090836.4024-1-contrib@steffen-goertz.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 88.198.119.201 Subject: [Qemu-devel] [PATCH 3/7] arm: Add chip variant property to nRF51 SoC X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Jim Mussared , Stefan Hajnoczi , =?UTF-8?q?Steffen=20G=C3=B6rtz?= , qemu-arm@nongnu.org, Joel Stanley , Julia Suvorova Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Nordic Semiconductor nRF51 SOCs are available in different "variants" which differ in available memory. This patchs adds a "variant" attribute to the SOC so that the user can choose between different variants and thus memory sizes. See product specification http://infocenter.nordicsemi.com/pdf/nRF51822_PS_= v3.1.pdf section 10.6 Signed-off-by: Steffen G=C3=B6rtz --- hw/arm/microbit.c | 4 ++-- hw/arm/nrf51_soc.c | 40 +++++++++++++++++++++++++++----------- include/hw/arm/nrf51_soc.h | 15 +++++++++++--- 3 files changed, 43 insertions(+), 16 deletions(-) diff --git a/hw/arm/microbit.c b/hw/arm/microbit.c index 8f3c446f52..d6776dea0a 100644 --- a/hw/arm/microbit.c +++ b/hw/arm/microbit.c @@ -27,11 +27,11 @@ static void microbit_init(MachineState *machine) object_property_add_child(OBJECT(machine), "nrf51", soc, &error_fatal); object_property_set_link(soc, OBJECT(system_memory), "memory", &error_abort); + qdev_prop_set_uint32(DEVICE(soc), "variant", NRF51_VARIANT_AA); =20 object_property_set_bool(soc, true, "realized", &error_abort); =20 - armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, - NRF51_SOC(soc)->flash_size); + armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, 0x00); } =20 =20 diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c index 441d05e1ef..85bce2c1e0 100644 --- a/hw/arm/nrf51_soc.c +++ b/hw/arm/nrf51_soc.c @@ -32,15 +32,21 @@ #define FLASH_BASE 0x00000000 #define SRAM_BASE 0x20000000 =20 -/* The size and base is for the NRF51822 part. If other parts - * are supported in the future, add a sub-class of NRF51SoC for - * the specific variants */ -#define NRF51822_FLASH_SIZE (256 * 1024) -#define NRF51822_SRAM_SIZE (16 * 1024) +#define PAGE_SIZE 1024 =20 /* IRQ lines can be derived from peripheral base addresses */ #define BASE_TO_IRQ(base) (((base) >> 12) & 0x1F) =20 +/* RAM and CODE size in number of pages for different NRF51Variants varian= ts */ +struct { + hwaddr ram_size; + hwaddr flash_size; +} NRF51VariantAttributes[] =3D { + [NRF51_VARIANT_AA] =3D {.ram_size =3D 16, .flash_size =3D 256 }, + [NRF51_VARIANT_AB] =3D {.ram_size =3D 16, .flash_size =3D 128 }, + [NRF51_VARIANT_AC] =3D {.ram_size =3D 32, .flash_size =3D 256 }, +}; + static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp) { NRF51State *s =3D NRF51_SOC(dev_soc); @@ -51,13 +57,21 @@ static void nrf51_soc_realize(DeviceState *dev_soc, Err= or **errp) return; } =20 + if (!(s->part_variant > NRF51_VARIANT_INVALID + && s->part_variant < NRF51_VARIANT_MAX)) { + error_setg(errp, "VARIANT not set or invalid"); + return; + } + object_property_set_link(OBJECT(&s->cpu), OBJECT(&s->container), "memo= ry", &err); object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err); =20 memory_region_add_subregion_overlap(&s->container, 0, s->board_memory,= -1); =20 - memory_region_init_ram(&s->flash, OBJECT(s), "nrf51.flash", s->flash_s= ize, + /* FLASH */ + memory_region_init_ram(&s->flash, NULL, "nrf51_soc.flash", + NRF51VariantAttributes[s->part_variant].flash_size * PAGE_SIZE, &err); if (err) { error_propagate(errp, err); @@ -66,7 +80,9 @@ static void nrf51_soc_realize(DeviceState *dev_soc, Error= **errp) memory_region_set_readonly(&s->flash, true); memory_region_add_subregion(&s->container, FLASH_BASE, &s->flash); =20 - memory_region_init_ram(&s->sram, NULL, "nrf51.sram", s->sram_size, &er= r); + /* SRAM */ + memory_region_init_ram(&s->sram, NULL, "nrf51_soc.sram", + NRF51VariantAttributes[s->part_variant].ram_size * PAGE_SIZE, = &err); if (err) { error_propagate(errp, err); return; @@ -85,17 +101,19 @@ static void nrf51_soc_init(Object *obj) memory_region_init(&s->container, obj, "nrf51-container", UINT64_MAX); =20 object_initialize(&s->cpu, sizeof(s->cpu), TYPE_ARMV7M); - object_property_add_child(OBJECT(s), "armv6m", OBJECT(&s->cpu), &error= _abort); + object_property_add_child(OBJECT(s), "armv6m", OBJECT(&s->cpu), + &error_abort); qdev_set_parent_bus(DEVICE(&s->cpu), sysbus_get_default()); - qdev_prop_set_string(DEVICE(&s->cpu), "cpu-type", ARM_CPU_TYPE_NAME("c= ortex-m0")); + qdev_prop_set_string(DEVICE(&s->cpu), "cpu-type", + ARM_CPU_TYPE_NAME("cortex-m0")); qdev_prop_set_uint32(DEVICE(&s->cpu), "num-irq", 32); } =20 static Property nrf51_soc_properties[] =3D { DEFINE_PROP_LINK("memory", NRF51State, board_memory, TYPE_MEMORY_REGIO= N, MemoryRegion *), - DEFINE_PROP_UINT32("sram-size", NRF51State, sram_size, NRF51822_SRAM_S= IZE), - DEFINE_PROP_UINT32("flash-size", NRF51State, flash_size, NRF51822_FLAS= H_SIZE), + DEFINE_PROP_INT32("variant", NRF51State, part_variant, + NRF51_VARIANT_INVALID), DEFINE_PROP_END_OF_LIST(), }; =20 diff --git a/include/hw/arm/nrf51_soc.h b/include/hw/arm/nrf51_soc.h index e380ec26b8..24212f9174 100644 --- a/include/hw/arm/nrf51_soc.h +++ b/include/hw/arm/nrf51_soc.h @@ -29,14 +29,23 @@ typedef struct NRF51State { MemoryRegion sram; MemoryRegion flash; =20 - uint32_t sram_size; - uint32_t flash_size; - MemoryRegion *board_memory; =20 MemoryRegion container; =20 + /* Properties */ + int32_t part_variant; } NRF51State; =20 + +/* Variants as described in nRF51 product specification section 10.6 table= 73 */ +typedef enum { + NRF51_VARIANT_INVALID =3D -1, + NRF51_VARIANT_AA =3D 0, + NRF51_VARIANT_AB =3D 1, + NRF51_VARIANT_AC =3D 2, + NRF51_VARIANT_MAX =3D 3 +} NRF51Variants; + #endif =20 --=20 2.18.0 From nobody Tue May 7 22:50:33 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1533978675942119.02900714426517; Sat, 11 Aug 2018 02:11:15 -0700 (PDT) Received: from localhost ([::1]:59377 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1foPvT-0008CZ-FY for importer@patchew.org; Sat, 11 Aug 2018 05:11:11 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55089) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1foPtD-0005u7-Il for qemu-devel@nongnu.org; Sat, 11 Aug 2018 05:08:52 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1foPtC-0001Jf-AS for qemu-devel@nongnu.org; Sat, 11 Aug 2018 05:08:51 -0400 Received: from steffen-goertz.de ([88.198.119.201]:34700) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1foPt9-0001Ev-QT; Sat, 11 Aug 2018 05:08:47 -0400 Received: from localhost.localdomain (tmo-080-6.customers.d1-online.com [80.187.80.6]) by steffen-goertz.de (Postfix) with ESMTPSA id 000D94BBA9; Sat, 11 Aug 2018 11:05:38 +0200 (CEST) From: =?UTF-8?q?Steffen=20G=C3=B6rtz?= To: qemu-devel@nongnu.org Date: Sat, 11 Aug 2018 11:08:33 +0200 Message-Id: <20180811090836.4024-5-contrib@steffen-goertz.de> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180811090836.4024-1-contrib@steffen-goertz.de> References: <20180811090836.4024-1-contrib@steffen-goertz.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 88.198.119.201 Subject: [Qemu-devel] [PATCH 4/7] arm: Add additional datasheets and copyright lines X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Jim Mussared , Stefan Hajnoczi , =?UTF-8?q?Steffen=20G=C3=B6rtz?= , qemu-arm@nongnu.org, Joel Stanley , Julia Suvorova Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" This patch adds a link to the product specification which contain additional information about the Nordic Semiconductor nRF51 SOC series. Furthermore it adds a copyright line to all files that get changed significantly. Signed-off-by: Steffen G=C3=B6rtz --- hw/arm/microbit.c | 1 + hw/arm/nrf51_soc.c | 4 +++- include/hw/arm/nrf51_soc.h | 1 + 3 files changed, 5 insertions(+), 1 deletion(-) diff --git a/hw/arm/microbit.c b/hw/arm/microbit.c index d6776dea0a..bb6ddb6a79 100644 --- a/hw/arm/microbit.c +++ b/hw/arm/microbit.c @@ -3,6 +3,7 @@ * http://tech.microbit.org/hardware/ * * Copyright 2018 Joel Stanley + * Copyright 2018 Steffen G=C3=B6rtz * * This code is licensed under the GPL version 2 or later. See * the COPYING file in the top-level directory. diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c index 85bce2c1e0..2265d30352 100644 --- a/hw/arm/nrf51_soc.c +++ b/hw/arm/nrf51_soc.c @@ -1,8 +1,10 @@ /* * Nordic Semiconductor nRF51 SoC - * http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.1.pdf + * Reference Manual: http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.pdf + * Product Spec: http://infocenter.nordicsemi.com/pdf/nRF51822_PS_v3.1.pdf * * Copyright 2018 Joel Stanley + * Copyright 2018 Steffen G=C3=B6rtz * * This code is licensed under the GPL version 2 or later. See * the COPYING file in the top-level directory. diff --git a/include/hw/arm/nrf51_soc.h b/include/hw/arm/nrf51_soc.h index 24212f9174..45d9671dc3 100644 --- a/include/hw/arm/nrf51_soc.h +++ b/include/hw/arm/nrf51_soc.h @@ -2,6 +2,7 @@ * Nordic Semiconductor nRF51 SoC * * Copyright 2018 Joel Stanley + * Copyright 2018 Steffen G=C3=B6rtz * * This code is licensed under the GPL version 2 or later. See * the COPYING file in the top-level directory. --=20 2.18.0 From nobody Tue May 7 22:50:33 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1533978667124229.38844114463654; Sat, 11 Aug 2018 02:11:07 -0700 (PDT) Received: from localhost ([::1]:59374 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1foPvH-0007xm-3K for importer@patchew.org; Sat, 11 Aug 2018 05:10:59 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55091) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1foPtD-0005uA-Kh for qemu-devel@nongnu.org; Sat, 11 Aug 2018 05:08:52 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1foPtC-0001KP-V5 for qemu-devel@nongnu.org; Sat, 11 Aug 2018 05:08:51 -0400 Received: from steffen-goertz.de ([88.198.119.201]:34708) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1foPtA-0001Gc-TA; Sat, 11 Aug 2018 05:08:49 -0400 Received: from localhost.localdomain (tmo-080-6.customers.d1-online.com [80.187.80.6]) by steffen-goertz.de (Postfix) with ESMTPSA id 83F7B4BBAF; Sat, 11 Aug 2018 11:05:40 +0200 (CEST) From: =?UTF-8?q?Steffen=20G=C3=B6rtz?= To: qemu-devel@nongnu.org Date: Sat, 11 Aug 2018 11:08:34 +0200 Message-Id: <20180811090836.4024-6-contrib@steffen-goertz.de> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180811090836.4024-1-contrib@steffen-goertz.de> References: <20180811090836.4024-1-contrib@steffen-goertz.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 88.198.119.201 Subject: [Qemu-devel] [PATCH 5/7] arm: Improve error propagation in nRF51 SOC X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Jim Mussared , Stefan Hajnoczi , =?UTF-8?q?Steffen=20G=C3=B6rtz?= , qemu-arm@nongnu.org, Joel Stanley , Julia Suvorova Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" This patch takes care that errors that occur during instantiation of the cortex-m0 cpu are properly propagated. Signed-off-by: Steffen G=C3=B6rtz --- hw/arm/nrf51_soc.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c index 2265d30352..88a848de8b 100644 --- a/hw/arm/nrf51_soc.c +++ b/hw/arm/nrf51_soc.c @@ -66,8 +66,17 @@ static void nrf51_soc_realize(DeviceState *dev_soc, Erro= r **errp) } =20 object_property_set_link(OBJECT(&s->cpu), OBJECT(&s->container), "memo= ry", - &err); - object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err); + &err); + if (err) { + error_propagate(errp, err); + return; + } + object_property_set_bool(OBJECT(&s->cpu), true, "realized", + &err); + if (err) { + error_propagate(errp, err); + return; + } =20 memory_region_add_subregion_overlap(&s->container, 0, s->board_memory,= -1); =20 --=20 2.18.0 From nobody Tue May 7 22:50:33 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1533978845290607.8959656190564; Sat, 11 Aug 2018 02:14:05 -0700 (PDT) Received: from localhost ([::1]:59390 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1foPyG-000221-4f for importer@patchew.org; Sat, 11 Aug 2018 05:14:04 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55161) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1foPtK-000610-Sv for qemu-devel@nongnu.org; Sat, 11 Aug 2018 05:09:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1foPtG-0001PY-TG for qemu-devel@nongnu.org; Sat, 11 Aug 2018 05:08:58 -0400 Received: from steffen-goertz.de ([88.198.119.201]:34724) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1foPtC-0001Ja-Ev; Sat, 11 Aug 2018 05:08:50 -0400 Received: from localhost.localdomain (tmo-080-6.customers.d1-online.com [80.187.80.6]) by steffen-goertz.de (Postfix) with ESMTPSA id 94FB54BBB3; Sat, 11 Aug 2018 11:05:41 +0200 (CEST) From: =?UTF-8?q?Steffen=20G=C3=B6rtz?= To: qemu-devel@nongnu.org Date: Sat, 11 Aug 2018 11:08:35 +0200 Message-Id: <20180811090836.4024-7-contrib@steffen-goertz.de> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180811090836.4024-1-contrib@steffen-goertz.de> References: <20180811090836.4024-1-contrib@steffen-goertz.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 88.198.119.201 Subject: [Qemu-devel] [PATCH 6/7] arm: Instantiate nRF51 peripherals X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Jim Mussared , Stefan Hajnoczi , =?UTF-8?q?Steffen=20G=C3=B6rtz?= , qemu-arm@nongnu.org, Joel Stanley , Julia Suvorova Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Instantiate NVMs, NVMC, UART, RNG, GPIO and TIMERs. Signed-off-by: Steffen G=C3=B6rtz --- hw/arm/nrf51_soc.c | 153 +++++++++++++++++++++++++++++++++++-- include/hw/arm/nrf51_soc.h | 16 +++- 2 files changed, 161 insertions(+), 8 deletions(-) diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c index 88a848de8b..a395d3a00d 100644 --- a/hw/arm/nrf51_soc.c +++ b/hw/arm/nrf51_soc.c @@ -25,15 +25,20 @@ =20 #include "hw/arm/nrf51_soc.h" =20 -#define IOMEM_BASE 0x40000000 -#define IOMEM_SIZE 0x20000000 - -#define FICR_BASE 0x10000000 -#define FICR_SIZE 0x000000fc - #define FLASH_BASE 0x00000000 +#define FICR_BASE 0x10000000 +#define UICR_BASE 0x10001000 #define SRAM_BASE 0x20000000 =20 +#define IOMEM_BASE 0x40000000 +#define IOMEM_SIZE 0x20000000 + +#define UART_BASE 0x40002000 +#define TIMER_BASE 0x40008000 +#define RNG_BASE 0x4000D000 +#define NVMC_BASE 0x4001E000 +#define GPIO_BASE 0x50000000 + #define PAGE_SIZE 1024 =20 /* IRQ lines can be derived from peripheral base addresses */ @@ -49,10 +54,33 @@ struct { [NRF51_VARIANT_AC] =3D {.ram_size =3D 32, .flash_size =3D 256 }, }; =20 + +static uint64_t clock_read(void *opaque, hwaddr addr, unsigned int size) +{ + qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " [%u]\n", + __func__, addr, size); + return 1; +} + +static void clock_write(void *opaque, hwaddr addr, uint64_t data, + unsigned int size) +{ + qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " <- 0x%" PRIx64 " [%u]= \n", + __func__, addr, data, size); +} + +static const MemoryRegionOps clock_ops =3D { + .read =3D clock_read, + .write =3D clock_write +}; + static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp) { NRF51State *s =3D NRF51_SOC(dev_soc); Error *err =3D NULL; + MemoryRegion *mr =3D NULL; + size_t i; + qemu_irq irq; =20 if (!s->board_memory) { error_setg(errp, "memory property was not set"); @@ -100,14 +128,102 @@ static void nrf51_soc_realize(DeviceState *dev_soc, = Error **errp) } memory_region_add_subregion(&s->container, SRAM_BASE, &s->sram); =20 + + /* UART */ + qdev_prop_set_chr(DEVICE(&s->uart), "chardev", serial_hd(0)); + object_property_set_bool(OBJECT(&s->uart), true, "realized", &err); + if (err) { + error_propagate(errp, err); + return; + } + + mr =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->uart), 0); + memory_region_add_subregion_overlap(&s->container, UART_BASE, mr, 0); + irq =3D qdev_get_gpio_in(DEVICE(&s->cpu), BASE_TO_IRQ(UART_BASE)); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart), 0, irq); + + /* TIMER */ + for (i =3D 0; i < NRF51_TIMER_NUM; i++) { + object_property_set_bool(OBJECT(&s->timer[i]), true, "realized", &= err); + if (err) { + error_propagate(errp, err); + return; + } + + sysbus_mmio_map(SYS_BUS_DEVICE(&s->timer[i]), 0, + TIMER_BASE + i * 0x1000); + + irq =3D qdev_get_gpio_in(DEVICE(&s->cpu), + BASE_TO_IRQ(TIMER_BASE + i * 0x1000)); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer[i]), 0, irq); + } + + /* NVMC */ + object_property_set_link(OBJECT(&s->nvm), OBJECT(&s->container), + "memory", &err); + if (err) { + error_propagate(errp, err); + return; + } + object_property_set_uint(OBJECT(&s->nvm), + NRF51VariantAttributes[s->part_variant].flash_size, "code_size= ", + &err); + if (err) { + error_propagate(errp, err); + return; + } + object_property_set_bool(OBJECT(&s->nvm), true, "realized", &err); + if (err) { + error_propagate(errp, err); + return; + } + + mr =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->nvm), 0); + memory_region_add_subregion_overlap(&s->container, NVMC_BASE, mr, 0); + mr =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->nvm), 1); + memory_region_add_subregion_overlap(&s->container, FICR_BASE, mr, 0); + mr =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->nvm), 2); + memory_region_add_subregion_overlap(&s->container, UICR_BASE, mr, 0); + + /* RNG */ + object_property_set_bool(OBJECT(&s->rng), true, "realized", &err); + if (err) { + error_propagate(errp, err); + return; + } + + mr =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->rng), 0); + memory_region_add_subregion_overlap(&s->container, RNG_BASE, mr, 0); + irq =3D qdev_get_gpio_in(DEVICE(&s->cpu), BASE_TO_IRQ(RNG_BASE)); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->rng), 0, irq); + + /* GPIO */ + object_property_set_bool(OBJECT(&s->gpio), true, "realized", &err); + if (err) { + error_propagate(errp, err); + return; + } + + mr =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gpio), 0); + memory_region_add_subregion_overlap(&s->container, GPIO_BASE, mr, 0); + + /* Pass all GPIOs to the SOC layer so they are available to the board = */ + qdev_pass_gpios(DEVICE(&s->gpio), dev_soc, NULL); + + /* STUB Peripherals */ + memory_region_init_io(&s->clock, NULL, &clock_ops, NULL, + "nrf51_soc.clock", 0x1000); + memory_region_add_subregion_overlap(&s->container, IOMEM_BASE, &s->clo= ck, + -1); + create_unimplemented_device("nrf51_soc.io", IOMEM_BASE, IOMEM_SIZE); - create_unimplemented_device("nrf51_soc.ficr", FICR_BASE, FICR_SIZE); create_unimplemented_device("nrf51_soc.private", 0xF0000000, 0x1000000= 0); } =20 static void nrf51_soc_init(Object *obj) { NRF51State *s =3D NRF51_SOC(obj); + size_t i; =20 memory_region_init(&s->container, obj, "nrf51-container", UINT64_MAX); =20 @@ -118,6 +234,29 @@ static void nrf51_soc_init(Object *obj) qdev_prop_set_string(DEVICE(&s->cpu), "cpu-type", ARM_CPU_TYPE_NAME("cortex-m0")); qdev_prop_set_uint32(DEVICE(&s->cpu), "num-irq", 32); + + object_initialize(&s->uart, sizeof(s->uart), TYPE_NRF51_UART); + object_property_add_child(obj, "uart", OBJECT(&s->uart), &error_abort); + qdev_set_parent_bus(DEVICE(&s->uart), sysbus_get_default()); + + object_initialize(&s->nvm, sizeof(s->nvm), TYPE_NRF51_NVM); + object_property_add_child(obj, "nvm", OBJECT(&s->nvm), &error_abort); + qdev_set_parent_bus(DEVICE(&s->nvm), sysbus_get_default()); + + object_initialize(&s->rng, sizeof(s->rng), TYPE_NRF51_RNG); + object_property_add_child(obj, "rng", OBJECT(&s->rng), &error_abort); + qdev_set_parent_bus(DEVICE(&s->rng), sysbus_get_default()); + + object_initialize(&s->gpio, sizeof(s->gpio), TYPE_NRF51_GPIO); + object_property_add_child(obj, "gpio", OBJECT(&s->gpio), &error_abort); + qdev_set_parent_bus(DEVICE(&s->gpio), sysbus_get_default()); + + for (i =3D 0; i < NRF51_TIMER_NUM; i++) { + object_initialize(&s->timer[i], sizeof(s->timer[i]), TYPE_NRF51_TI= MER); + object_property_add_child(obj, "timer[*]", OBJECT(&s->timer[i]), N= ULL); + qdev_set_parent_bus(DEVICE(&s->timer[i]), sysbus_get_default()); + } + } =20 static Property nrf51_soc_properties[] =3D { diff --git a/include/hw/arm/nrf51_soc.h b/include/hw/arm/nrf51_soc.h index 45d9671dc3..d47b42fa37 100644 --- a/include/hw/arm/nrf51_soc.h +++ b/include/hw/arm/nrf51_soc.h @@ -14,11 +14,18 @@ #include "qemu/osdep.h" #include "hw/sysbus.h" #include "hw/arm/armv7m.h" +#include "hw/char/nrf51_uart.h" +#include "hw/misc/nrf51_rng.h" +#include "hw/nvram/nrf51_nvm.h" +#include "hw/gpio/nrf51_gpio.h" +#include "hw/timer/nrf51_timer.h" =20 #define TYPE_NRF51_SOC "nrf51-soc" #define NRF51_SOC(obj) \ OBJECT_CHECK(NRF51State, (obj), TYPE_NRF51_SOC) =20 +#define NRF51_TIMER_NUM 3 + typedef struct NRF51State { /*< private >*/ SysBusDevice parent_obj; @@ -31,9 +38,16 @@ typedef struct NRF51State { MemoryRegion flash; =20 MemoryRegion *board_memory; - MemoryRegion container; =20 + MemoryRegion clock; + + Nrf51UART uart; + Nrf51NVMState nvm; + Nrf51RNGState rng; + Nrf51GPIOState gpio; + Nrf51TimerState timer[NRF51_TIMER_NUM]; + /* Properties */ int32_t part_variant; } NRF51State; --=20 2.18.0 From nobody Tue May 7 22:50:33 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1533978882624459.97206502469703; Sat, 11 Aug 2018 02:14:42 -0700 (PDT) Received: from localhost ([::1]:59392 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1foPyr-0002ZE-EJ for importer@patchew.org; Sat, 11 Aug 2018 05:14:41 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55162) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1foPtK-000611-T3 for qemu-devel@nongnu.org; Sat, 11 Aug 2018 05:09:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1foPtG-0001PT-Sk for qemu-devel@nongnu.org; Sat, 11 Aug 2018 05:08:58 -0400 Received: from steffen-goertz.de ([88.198.119.201]:34730) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1foPtD-0001Kz-JJ; Sat, 11 Aug 2018 05:08:51 -0400 Received: from localhost.localdomain (tmo-080-6.customers.d1-online.com [80.187.80.6]) by steffen-goertz.de (Postfix) with ESMTPSA id 271594BBB1; Sat, 11 Aug 2018 11:05:43 +0200 (CEST) From: =?UTF-8?q?Steffen=20G=C3=B6rtz?= To: qemu-devel@nongnu.org Date: Sat, 11 Aug 2018 11:08:36 +0200 Message-Id: <20180811090836.4024-8-contrib@steffen-goertz.de> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180811090836.4024-1-contrib@steffen-goertz.de> References: <20180811090836.4024-1-contrib@steffen-goertz.de> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 88.198.119.201 Subject: [Qemu-devel] [PATCH 7/7] arm: Instantiate Microbit board-level devices X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Jim Mussared , Stefan Hajnoczi , =?UTF-8?q?Steffen=20G=C3=B6rtz?= , qemu-arm@nongnu.org, Joel Stanley , Julia Suvorova Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Instantiate the LED matrix and set board-level pull-up default values to buttons A and B. This is necessary to calm down the microsoft pxt javascript runtime available for the micro:bit. Signed-off-by: Steffen G=C3=B6rtz --- hw/arm/microbit.c | 52 ++++++++++++++++++++++++++++++++++----- include/hw/arm/microbit.h | 1 + 2 files changed, 47 insertions(+), 6 deletions(-) diff --git a/hw/arm/microbit.c b/hw/arm/microbit.c index bb6ddb6a79..6fad0de2cd 100644 --- a/hw/arm/microbit.c +++ b/hw/arm/microbit.c @@ -13,34 +13,74 @@ #include "qapi/error.h" #include "hw/boards.h" #include "hw/arm/arm.h" +#include "sysemu/qtest.h" #include "exec/address-spaces.h" =20 #include "hw/arm/microbit.h" =20 +#define BUTTON_A_PIN 17 +#define BUTTON_B_PIN 26 + static void microbit_init(MachineState *machine) { MicrobitMachineState *s =3D MICROBIT_MACHINE(machine); MemoryRegion *system_memory =3D get_system_memory(); - Object *soc; + DeviceState *soc, *matrix; =20 object_initialize(&s->nrf51, sizeof(s->nrf51), TYPE_NRF51_SOC); - soc =3D OBJECT(&s->nrf51); - object_property_add_child(OBJECT(machine), "nrf51", soc, &error_fatal); - object_property_set_link(soc, OBJECT(system_memory), + soc =3D DEVICE(&s->nrf51); + object_property_add_child(OBJECT(machine), "nrf51", OBJECT(soc), + &error_fatal); + object_property_set_link(OBJECT(soc), OBJECT(system_memory), "memory", &error_abort); - qdev_prop_set_uint32(DEVICE(soc), "variant", NRF51_VARIANT_AA); + qdev_prop_set_uint32(soc, "variant", NRF51_VARIANT_AA); =20 - object_property_set_bool(soc, true, "realized", &error_abort); + object_property_set_bool(OBJECT(soc), true, "realized", &error_abort); + + object_initialize(&s->matrix, sizeof(s->matrix), TYPE_LED_MATRIX); + matrix =3D DEVICE(&s->matrix); + qdev_prop_set_uint16(matrix, "rows", 3); + qdev_prop_set_uint16(matrix, "cols", 9); + object_property_set_bool(OBJECT(matrix), true, "realized", &error_fata= l); + + qdev_connect_gpio_out(soc, 4, qdev_get_gpio_in_named(matrix, "col", 0)= ); + qdev_connect_gpio_out(soc, 5, qdev_get_gpio_in_named(matrix, "col", 1)= ); + qdev_connect_gpio_out(soc, 6, qdev_get_gpio_in_named(matrix, "col", 2)= ); + qdev_connect_gpio_out(soc, 7, qdev_get_gpio_in_named(matrix, "col", 3)= ); + qdev_connect_gpio_out(soc, 8, qdev_get_gpio_in_named(matrix, "col", 4)= ); + qdev_connect_gpio_out(soc, 9, qdev_get_gpio_in_named(matrix, "col", 5)= ); + qdev_connect_gpio_out(soc, 10, qdev_get_gpio_in_named(matrix, "col", 6= )); + qdev_connect_gpio_out(soc, 11, qdev_get_gpio_in_named(matrix, "col", 7= )); + qdev_connect_gpio_out(soc, 12, qdev_get_gpio_in_named(matrix, "col", 8= )); + + qdev_connect_gpio_out(soc, 13, qdev_get_gpio_in_named(matrix, "row", 0= )); + qdev_connect_gpio_out(soc, 14, qdev_get_gpio_in_named(matrix, "row", 1= )); + qdev_connect_gpio_out(soc, 15, qdev_get_gpio_in_named(matrix, "row", 2= )); =20 armv7m_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, 0x00); } =20 +static void microbit_reset(void) +{ + MachineState *machine =3D MACHINE(qdev_get_machine()); + MicrobitMachineState *s =3D MICROBIT_MACHINE(machine); + + qemu_devices_reset(); + + /* Board level pull-up */ + if (!qtest_enabled()) { + qemu_set_irq(qdev_get_gpio_in(DEVICE(&s->nrf51), BUTTON_A_PIN), 1); + qemu_set_irq(qdev_get_gpio_in(DEVICE(&s->nrf51), BUTTON_B_PIN), 1); + } +} + =20 static void microbit_machine_init(MachineClass *mc) { mc->desc =3D "BBC micro:bit"; mc->init =3D microbit_init; mc->max_cpus =3D 1; + mc->reset =3D microbit_reset; } =20 static void microbit_machine_init_class_init(ObjectClass *oc, void *data) diff --git a/include/hw/arm/microbit.h b/include/hw/arm/microbit.h index 89f0c6bc07..094326b4ae 100644 --- a/include/hw/arm/microbit.h +++ b/include/hw/arm/microbit.h @@ -24,6 +24,7 @@ typedef struct MicrobitMachineState { MachineState parent_obj; =20 NRF51State nrf51; + LEDMatrixState matrix; } MicrobitMachineState; =20 #endif --=20 2.18.0