From nobody Wed Nov 5 10:47:07 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1533820418375780.8372953518249; Thu, 9 Aug 2018 06:13:38 -0700 (PDT) Received: from localhost ([::1]:50772 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fnkkz-0000Xl-3Z for importer@patchew.org; Thu, 09 Aug 2018 09:13:37 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47434) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fnkZe-000680-F9 for qemu-devel@nongnu.org; Thu, 09 Aug 2018 09:01:55 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fnkZU-0003S8-OB for qemu-devel@nongnu.org; Thu, 09 Aug 2018 09:01:54 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:44220) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fnkZG-0003Hp-CR; Thu, 09 Aug 2018 09:01:30 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fnkZF-0003Jc-Ba; Thu, 09 Aug 2018 14:01:29 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Thu, 9 Aug 2018 14:01:10 +0100 Message-Id: <20180809130115.28951-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180809130115.28951-1-peter.maydell@linaro.org> References: <20180809130115.28951-1-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH 11/16] hw/dma/pl080: Support all three interrupt lines X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RDMRC_1 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The PL080 and PL081 have three outgoing interrupt lines: * DMACINTERR signals DMA errors * DMACINTTC is the DMA count interrupt * DMACINTR is a combined interrupt, the logical OR of the other two We currently only implement DMACINTR, because that's all the realview and versatile boards needed, but the instances of the PL081 in the MPS2 firmware images use all three interrupt lines. Implement the missing DMACINTERR and DMACINTTC. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/dma/pl080.h | 6 +++++- hw/dma/pl080.c | 13 ++++++++----- 2 files changed, 13 insertions(+), 6 deletions(-) diff --git a/include/hw/dma/pl080.h b/include/hw/dma/pl080.h index 7deb46c8578..7c6a4184833 100644 --- a/include/hw/dma/pl080.h +++ b/include/hw/dma/pl080.h @@ -17,7 +17,9 @@ * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0218e/DDI0218.pdf * * QEMU interface: - * + sysbus IRQ: DMACINTR combined interrupt line + * + sysbus IRQ 0: DMACINTR combined interrupt line + * + sysbus IRQ 1: DMACINTERR error interrupt request + * + sysbus IRQ 2: DMACINTTC count interrupt request * + sysbus MMIO region 0: MemoryRegion for the device's registers */ =20 @@ -57,6 +59,8 @@ typedef struct PL080State { /* Flag to avoid recursive DMA invocations. */ int running; qemu_irq irq; + qemu_irq interr; + qemu_irq inttc; } PL080State; =20 #endif diff --git a/hw/dma/pl080.c b/hw/dma/pl080.c index 0f79c2d8a6c..301030dd118 100644 --- a/hw/dma/pl080.c +++ b/hw/dma/pl080.c @@ -75,11 +75,12 @@ static const unsigned char pl081_id[] =3D =20 static void pl080_update(PL080State *s) { - if ((s->tc_int & s->tc_mask) - || (s->err_int & s->err_mask)) - qemu_irq_raise(s->irq); - else - qemu_irq_lower(s->irq); + bool tclevel =3D (s->tc_int & s->tc_mask); + bool errlevel =3D (s->err_int & s->err_mask); + + qemu_set_irq(s->interr, errlevel); + qemu_set_irq(s->inttc, tclevel); + qemu_set_irq(s->irq, errlevel || tclevel); } =20 static void pl080_run(PL080State *s) @@ -352,6 +353,8 @@ static void pl080_init(Object *obj) memory_region_init_io(&s->iomem, OBJECT(s), &pl080_ops, s, "pl080", 0x= 1000); sysbus_init_mmio(sbd, &s->iomem); sysbus_init_irq(sbd, &s->irq); + sysbus_init_irq(sbd, &s->interr); + sysbus_init_irq(sbd, &s->inttc); s->nchannels =3D 8; } =20 --=20 2.17.1