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[97.113.8.179]) by smtp.gmail.com with ESMTPSA id m30-v6sm7355799pff.121.2018.08.08.21.22.18 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 08 Aug 2018 21:22:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=iPTMcFpTowzzeR3AA8m0CxGcQ3PcWy1tCYbypW7plhs=; b=RnkwxGB9pyCnDTdyOHHhZhDWwbMvV9USJ+alu1vyr2HUx/P4qkLr9YWikNlXDuO6gO w+DXWLEO2UjiLhHqd3qD0YJt5l7De58U+ehfwS1O6YlBh7I3P7GG3FK9yAjHC7AVEgx9 XdI1LccGqmh6Bf1q6X2Q3VG2PJKHL8rKd1cDE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=iPTMcFpTowzzeR3AA8m0CxGcQ3PcWy1tCYbypW7plhs=; b=nSS8cMvPiqsbs/lXl1mcmnx1UwQR+kXiNfaps5xlPRDWFlXKnV6EjLnFVcatadrrq6 NG0DmgMG5vUA5JDDyIgY7VxsHcP1x3dujp0hP393lNqgE2XJPw5X8fI80ex0/ERJm/gT D+6W7q7DunVMX3u+OaeiK+kLwyZCFz9KUJ/G4FEl4/paq2YRcTm7DlEa65+YomczPZvn 3h9tNrz3+Q/m1QKDzbQLAo1VcAGw+wEU8mxn1MmnVFKtuKjtAzpQ+zawZHrBvtgHkOqw yH8rtBIAwKU7kiWyDzxv9kTF8Ozi38fyHYG1tnbxYDXYUBR8a55RQZ4yzaMvBngWJNaf kzPw== X-Gm-Message-State: AOUpUlH0hlTkB+e2jH47cLTRpluuG8CfTvXv4sx4ow8UVrdqR2UvlfAA R6FYX0x0cKMFUVW5FvsbtLwY1dQf6Yk= X-Google-Smtp-Source: AA+uWPwsY33+v+sfn53CFPSsi9rn7yl0BVE4vCV/OnJYjeVHxTXK7J50N2U7QniEnGlf/eYQiaAp4A== X-Received: by 2002:a17:902:26c:: with SMTP id 99-v6mr466624plc.341.1533788539995; Wed, 08 Aug 2018 21:22:19 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 8 Aug 2018 21:21:54 -0700 Message-Id: <20180809042206.15726-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180809042206.15726-1-richard.henderson@linaro.org> References: <20180809042206.15726-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::242 Subject: [Qemu-devel] [PATCH 08/20] target/arm: Pass in current_el to fp and sve_exception_el X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent.desnogues@gmail.com, peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" We are going to want to determine whether sve is enabled for EL than current. Signed-off-by: Richard Henderson --- target/arm/helper.c | 21 +++++++++------------ 1 file changed, 9 insertions(+), 12 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 26e9098c5f..290b1a849e 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4344,12 +4344,10 @@ static const ARMCPRegInfo debug_lpae_cp_reginfo[] = =3D { * take care of raising that exception. * C.f. the ARM pseudocode function CheckSVEEnabled. */ -static int sve_exception_el(CPUARMState *env) +static int sve_exception_el(CPUARMState *env, int el) { #ifndef CONFIG_USER_ONLY - unsigned current_el =3D arm_current_el(env); - - if (current_el <=3D 1) { + if (el <=3D 1) { bool disabled =3D false; =20 /* The CPACR.ZEN controls traps to EL1: @@ -4360,7 +4358,7 @@ static int sve_exception_el(CPUARMState *env) if (!extract32(env->cp15.cpacr_el1, 16, 1)) { disabled =3D true; } else if (!extract32(env->cp15.cpacr_el1, 17, 1)) { - disabled =3D current_el =3D=3D 0; + disabled =3D el =3D=3D 0; } if (disabled) { /* route_to_el2 */ @@ -4373,7 +4371,7 @@ static int sve_exception_el(CPUARMState *env) if (!extract32(env->cp15.cpacr_el1, 20, 1)) { disabled =3D true; } else if (!extract32(env->cp15.cpacr_el1, 21, 1)) { - disabled =3D current_el =3D=3D 0; + disabled =3D el =3D=3D 0; } if (disabled) { return 0; @@ -4383,7 +4381,7 @@ static int sve_exception_el(CPUARMState *env) /* CPTR_EL2. Since TZ and TFP are positive, * they will be zero when EL2 is not present. */ - if (current_el <=3D 2 && !arm_is_secure_below_el3(env)) { + if (el <=3D 2 && !arm_is_secure_below_el3(env)) { if (env->cp15.cptr_el[2] & CPTR_TZ) { return 2; } @@ -12318,11 +12316,10 @@ uint32_t HELPER(crc32c)(uint32_t acc, uint32_t va= l, uint32_t bytes) /* Return the exception level to which FP-disabled exceptions should * be taken, or 0 if FP is enabled. */ -static inline int fp_exception_el(CPUARMState *env) +static int fp_exception_el(CPUARMState *env, int cur_el) { #ifndef CONFIG_USER_ONLY int fpen; - int cur_el =3D arm_current_el(env); =20 /* CPACR and the CPTR registers don't exist before v6, so FP is * always accessible @@ -12385,11 +12382,12 @@ void cpu_get_tb_cpu_state(CPUARMState *env, targe= t_ulong *pc, target_ulong *cs_base, uint32_t *pflags) { ARMMMUIdx mmu_idx =3D core_to_arm_mmu_idx(env, cpu_mmu_index(env, fals= e)); - int fp_el =3D fp_exception_el(env); + int current_el =3D arm_current_el(env); + int fp_el =3D fp_exception_el(env, current_el); uint32_t flags; =20 if (is_a64(env)) { - int sve_el =3D sve_exception_el(env); + int sve_el =3D sve_exception_el(env, current_el); uint32_t zcr_len; =20 *pc =3D env->pc; @@ -12404,7 +12402,6 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_= ulong *pc, if (sve_el !=3D 0 && fp_el =3D=3D 0) { zcr_len =3D 0; } else { - int current_el =3D arm_current_el(env); ARMCPU *cpu =3D arm_env_get_cpu(env); =20 zcr_len =3D cpu->sve_max_vq - 1; --=20 2.17.1