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[97.113.8.179]) by smtp.gmail.com with ESMTPSA id m30-v6sm7355799pff.121.2018.08.08.21.22.10 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 08 Aug 2018 21:22:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=megdeTjYGDi91jW7S3Vt/13VC1dSMwSCHADtSBmt828=; b=OCfbar2s3AvvtrRP2flIyuJebUWgnz4OsnW0S0NCUTAnucXZcf8umReYanVR0GznoY dR7QZedSuwvcne4ZAaoLiKzJOWw/pFipah8nrwnf+d5szluxhEtmOfU047tPHtBy8Y6O IpdENAjxiNrQiSwXCwno1sIqbwaP2enuXtBEQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=megdeTjYGDi91jW7S3Vt/13VC1dSMwSCHADtSBmt828=; b=soJ+BSAUNXCdMmpu+YDun/NM0y51iZNPPKbWiXAedCFI63PS8BChxEFVXINXDwtRRx tmr7WzpFkeTCLH/V6n01CNYoyOmP9Rajfpgq2vL5BWFWR6+WQ33u4MdA9TFoVNrrh1ql yQ4DdSTFror2oljfak4cykl9oRKuyI6L1hLwl25kZIVHlg1s+MItQLDodpzjIqxBTOry v+f0GgJVrXEWSCpULwbelmU+vGrSpTh6Ix3h24vFyxWNSS2UC1BO/qEhDPp85r79pRND Z+n1iGJCqxQuBAB3ub5uGb1wFkpHlPmXW6biyvfBYbBIFjF6kJjpz0QualUjOs25Y4Jb YxPA== X-Gm-Message-State: AOUpUlFKmldz7tv4uRYxhK2OG3VdG+KT4K7xl5S2R7wccQY0+FAbfR1k x+IsEBV6YsvBYcH7ovSgrUzUtNtABjg= X-Google-Smtp-Source: AA+uWPzkY/UJ+6CySCMivjv+cCzUvsmt2RkYPXh3vAzPtfOmatxoYLpXbxyJeJ9a/azGFFJEYiOVHQ== X-Received: by 2002:a17:902:163:: with SMTP id 90-v6mr501677plb.322.1533788531458; Wed, 08 Aug 2018 21:22:11 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 8 Aug 2018 21:21:48 -0700 Message-Id: <20180809042206.15726-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180809042206.15726-1-richard.henderson@linaro.org> References: <20180809042206.15726-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::244 Subject: [Qemu-devel] [PATCH 02/20] target/arm: Set ID_AA64PFR0 bits for SVE for -cpu max X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent.desnogues@gmail.com, peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This it a hair out of spec in that we have and advertise, support for fp16 in aarch64 mode, but do not have nor advertise the same in aarch32 mode. Rationale as commented. Signed-off-by: Richard Henderson --- target/arm/cpu64.c | 21 +++++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 4d629bb99b..ae650b608e 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -282,15 +282,24 @@ static void aarch64_max_initfn(Object *obj) cpu->id_aa64isar1 =3D deposit64(cpu->id_aa64isar1, 16, 4, 1); cpu->id_isar5 =3D deposit32(cpu->id_isar5, 28, 4, 1); =20 -#ifdef CONFIG_USER_ONLY - /* We don't set these in system emulation mode for the moment, - * since we don't correctly set the ID registers to advertise them, - * and in some cases they're only available in AArch64 and not AAr= ch32, - * whereas the architecture requires them to be present in both if - * present in either. + /* TODO: This is not yet implemented for AArch32, whereas the + * architecture requires a feature to be present in both if + * it is present in either. However, it is required by SVE, + * so we don't want to leave it out of AArch64 state. + * + * Practically, the Linux kernel does not query the MVFR1 bit + * nor expose this as a HWCAP bit to AArch32 userland. Thus + * userland, if it wanted to use fp16, would have to probe for + * support by executing an insn and checking for SIGILL. + * At which point it will get the correct answer: unsupported. */ set_feature(&cpu->env, ARM_FEATURE_V8_FP16); + cpu->id_aa64pfr0 =3D deposit64(cpu->id_aa64pfr0, 20, 4, 1); + set_feature(&cpu->env, ARM_FEATURE_SVE); + cpu->id_aa64pfr0 =3D deposit64(cpu->id_aa64pfr0, 32, 4, 1); + +#ifdef CONFIG_USER_ONLY /* For usermode -cpu max we can use a larger and more efficient DCZ * blocksize since we don't have to follow what the hardware does. */ --=20 2.17.1