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[97.113.8.179]) by smtp.gmail.com with ESMTPSA id m30-v6sm7355799pff.121.2018.08.08.21.22.35 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 08 Aug 2018 21:22:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=m4fzpXRRelRwa/5HNltn2wYR+ly+65acDwTBZQuGGx0=; b=UvQa25tjs7HaNzUiDQd2qhmf6LbhRe5MtoyyAEBsaqoYSxEBxi4hVuz//5SF88mVME fxcadNJndjpxZmw+OxvXbA+te5LZKgQsBYCGpJk4+sohjCuzguYaUp0/OQYBOfQJfldH Ht2cikfIQN0PQs5niBRUvfxCwmK5lHLX3Gq8M= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=m4fzpXRRelRwa/5HNltn2wYR+ly+65acDwTBZQuGGx0=; b=ZDVuawKHFLcWLeAvIR1of9RSalyscUNRKM0wZ7qto3hoYTM5YUPIpJtFAqwAAOxfRp s0M/LpKzp949SdjjgKXhcHJYbjnZXhaU0i46Bk5/HPfFICwOjZPfeRBBF67Y+4AkgEtq Ofrf3joPQGtkMEdZVi4uOoiIxmovP3FVW6C+AmLtD7Ju2Z9klpT031Xb7N1ZB/TNaZ4g XtXzHksRLHeomnOoWgMIgQDZe0xwp1y/KBgHaxV1OTU28eWDPqyf728fx5C/55xvt/DH VgvYMbeJaKcmTvcjdJSTHjRbTjrodVVz14DeTEQO5yuUc0kyM8AFpuooVqx9WXoeMM7m MHMw== X-Gm-Message-State: AOUpUlFIzzZe/JAPMTJUnjJpZ1BzfGXfZnKp+J+vef+kzZ0h510kzyWF OE0Cjk9NS/hZ9pN9QNi5FIHr5CktzIg= X-Google-Smtp-Source: AA+uWPyam7lzxzTjgl8+GEQTk/3xLgiEjMabxW1i3/HfwI9y/9Blk11JXyMWxCh7uUWx7utNmLDqDg== X-Received: by 2002:a63:710d:: with SMTP id m13-v6mr530237pgc.66.1533788556993; Wed, 08 Aug 2018 21:22:36 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 8 Aug 2018 21:22:06 -0700 Message-Id: <20180809042206.15726-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180809042206.15726-1-richard.henderson@linaro.org> References: <20180809042206.15726-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::42a Subject: [Qemu-devel] [PATCH 20/20] target/arm: Pass TCGMemOpIdx to sve memory helpers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent.desnogues@gmail.com, peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" There is quite a lot of code required to compute cpu_mem_index, or even put together the full TCGMemOpIdx. This can easily be done at translation time. Signed-off-by: Richard Henderson --- target/arm/internals.h | 5 ++ target/arm/sve_helper.c | 138 +++++++++++++++++++------------------ target/arm/translate-sve.c | 67 +++++++++++------- 3 files changed, 121 insertions(+), 89 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index dc9357766c..24c0444c8d 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -796,4 +796,9 @@ static inline uint32_t arm_debug_exception_fsr(CPUARMSt= ate *env) } } =20 +/* Note make_memop_idx reserves 4 bits for mmu_idx, and MO_BSWAP is bit 3. + * Thus a TCGMemOpIdx, without any MO_ALIGN bits, fits in 8 bits. + */ +#define MEMOPIDX_SHIFT 8 + #endif diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index 6728862326..5bae600d17 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -19,6 +19,7 @@ =20 #include "qemu/osdep.h" #include "cpu.h" +#include "internals.h" #include "exec/exec-all.h" #include "exec/cpu_ldst.h" #include "exec/helper-proto.h" @@ -3986,7 +3987,7 @@ typedef intptr_t sve_ld1_host_fn(void *vd, void *vg, = void *host, * The controlling predicate is known to be true. */ typedef void sve_ld1_tlb_fn(CPUARMState *env, void *vd, intptr_t reg_off, - target_ulong vaddr, int mmu_idx, uintptr_t ra); + target_ulong vaddr, TCGMemOpIdx oi, uintptr_t = ra); typedef sve_ld1_tlb_fn sve_st1_tlb_fn; =20 /* @@ -4013,16 +4014,15 @@ static intptr_t sve_##NAME##_host(void *vd, void *v= g, void *host, \ #ifdef CONFIG_SOFTMMU #define DO_LD_TLB(NAME, H, TYPEE, TYPEM, HOST, MOEND, TLB) \ static void sve_##NAME##_tlb(CPUARMState *env, void *vd, intptr_t reg_off,= \ - target_ulong addr, int mmu_idx, uintptr_t ra)= \ + target_ulong addr, TCGMemOpIdx oi, uintptr_t = ra) \ { = \ - TCGMemOpIdx oi =3D make_memop_idx(ctz32(sizeof(TYPEM)) | MOEND, mmu_id= x); \ TYPEM val =3D TLB(env, addr, oi, ra); = \ *(TYPEE *)(vd + H(reg_off)) =3D val; = \ } #else #define DO_LD_TLB(NAME, H, TYPEE, TYPEM, HOST, MOEND, TLB) = \ static void sve_##NAME##_tlb(CPUARMState *env, void *vd, intptr_t reg_off,= \ - target_ulong addr, int mmu_idx, uintptr_t ra)= \ + target_ulong addr, TCGMemOpIdx oi, uintptr_t = ra) \ { = \ TYPEM val =3D HOST(g2h(addr)); = \ *(TYPEE *)(vd + H(reg_off)) =3D val; = \ @@ -4287,11 +4287,13 @@ static void sve_ld1_r(CPUARMState *env, void *vg, c= onst target_ulong addr, sve_ld1_host_fn *host_fn, sve_ld1_tlb_fn *tlb_fn) { - void *vd =3D &env->vfp.zregs[simd_data(desc)]; + const TCGMemOpIdx oi =3D extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHI= FT); + const int mmu_idx =3D get_mmuidx(oi); + const unsigned rd =3D extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT= , 5); + void *vd =3D &env->vfp.zregs[rd]; const int diffsz =3D esz - msz; const intptr_t reg_max =3D simd_oprsz(desc); const intptr_t mem_max =3D reg_max >> diffsz; - const int mmu_idx =3D cpu_mmu_index(env, false); ARMVectorReg scratch; void *host, *result; intptr_t split; @@ -4345,7 +4347,7 @@ static void sve_ld1_r(CPUARMState *env, void *vg, con= st target_ulong addr, * on I/O memory, it may succeed but not bring in the TLB entry. * But even then we have still made forward progress. */ - tlb_fn(env, result, reg_off, addr + mem_off, mmu_idx, retaddr); + tlb_fn(env, result, reg_off, addr + mem_off, oi, retaddr); reg_off +=3D 1 << esz; } #endif @@ -4406,9 +4408,9 @@ static void sve_ld2_r(CPUARMState *env, void *vg, tar= get_ulong addr, uint32_t desc, int size, uintptr_t ra, sve_ld1_tlb_fn *tlb_fn) { - const int mmu_idx =3D cpu_mmu_index(env, false); + const TCGMemOpIdx oi =3D extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHI= FT); + const unsigned rd =3D extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT= , 5); intptr_t i, oprsz =3D simd_oprsz(desc); - unsigned rd =3D simd_data(desc); ARMVectorReg scratch[2] =3D { }; =20 set_helper_retaddr(ra); @@ -4416,8 +4418,8 @@ static void sve_ld2_r(CPUARMState *env, void *vg, tar= get_ulong addr, uint16_t pg =3D *(uint16_t *)(vg + H1_2(i >> 3)); do { if (pg & 1) { - tlb_fn(env, &scratch[0], i, addr, mmu_idx, ra); - tlb_fn(env, &scratch[1], i, addr + size, mmu_idx, ra); + tlb_fn(env, &scratch[0], i, addr, oi, ra); + tlb_fn(env, &scratch[1], i, addr + size, oi, ra); } i +=3D size, pg >>=3D size; addr +=3D 2 * size; @@ -4434,9 +4436,9 @@ static void sve_ld3_r(CPUARMState *env, void *vg, tar= get_ulong addr, uint32_t desc, int size, uintptr_t ra, sve_ld1_tlb_fn *tlb_fn) { - const int mmu_idx =3D cpu_mmu_index(env, false); + const TCGMemOpIdx oi =3D extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHI= FT); + const unsigned rd =3D extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT= , 5); intptr_t i, oprsz =3D simd_oprsz(desc); - unsigned rd =3D simd_data(desc); ARMVectorReg scratch[3] =3D { }; =20 set_helper_retaddr(ra); @@ -4444,9 +4446,9 @@ static void sve_ld3_r(CPUARMState *env, void *vg, tar= get_ulong addr, uint16_t pg =3D *(uint16_t *)(vg + H1_2(i >> 3)); do { if (pg & 1) { - tlb_fn(env, &scratch[0], i, addr, mmu_idx, ra); - tlb_fn(env, &scratch[1], i, addr + size, mmu_idx, ra); - tlb_fn(env, &scratch[2], i, addr + 2 * size, mmu_idx, ra); + tlb_fn(env, &scratch[0], i, addr, oi, ra); + tlb_fn(env, &scratch[1], i, addr + size, oi, ra); + tlb_fn(env, &scratch[2], i, addr + 2 * size, oi, ra); } i +=3D size, pg >>=3D size; addr +=3D 3 * size; @@ -4464,9 +4466,9 @@ static void sve_ld4_r(CPUARMState *env, void *vg, tar= get_ulong addr, uint32_t desc, int size, uintptr_t ra, sve_ld1_tlb_fn *tlb_fn) { - const int mmu_idx =3D cpu_mmu_index(env, false); + const TCGMemOpIdx oi =3D extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHI= FT); + const unsigned rd =3D extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT= , 5); intptr_t i, oprsz =3D simd_oprsz(desc); - unsigned rd =3D simd_data(desc); ARMVectorReg scratch[4] =3D { }; =20 set_helper_retaddr(ra); @@ -4474,10 +4476,10 @@ static void sve_ld4_r(CPUARMState *env, void *vg, t= arget_ulong addr, uint16_t pg =3D *(uint16_t *)(vg + H1_2(i >> 3)); do { if (pg & 1) { - tlb_fn(env, &scratch[0], i, addr, mmu_idx, ra); - tlb_fn(env, &scratch[1], i, addr + size, mmu_idx, ra); - tlb_fn(env, &scratch[2], i, addr + 2 * size, mmu_idx, ra); - tlb_fn(env, &scratch[3], i, addr + 3 * size, mmu_idx, ra); + tlb_fn(env, &scratch[0], i, addr, oi, ra); + tlb_fn(env, &scratch[1], i, addr + size, oi, ra); + tlb_fn(env, &scratch[2], i, addr + 2 * size, oi, ra); + tlb_fn(env, &scratch[3], i, addr + 3 * size, oi, ra); } i +=3D size, pg >>=3D size; addr +=3D 4 * size; @@ -4572,11 +4574,13 @@ static void sve_ldff1_r(CPUARMState *env, void *vg,= const target_ulong addr, sve_ld1_host_fn *host_fn, sve_ld1_tlb_fn *tlb_fn) { - void *vd =3D &env->vfp.zregs[simd_data(desc)]; + const TCGMemOpIdx oi =3D extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHI= FT); + const int mmu_idx =3D get_mmuidx(oi); + const unsigned rd =3D extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT= , 5); + void *vd =3D &env->vfp.zregs[rd]; const int diffsz =3D esz - msz; const intptr_t reg_max =3D simd_oprsz(desc); const intptr_t mem_max =3D reg_max >> diffsz; - const int mmu_idx =3D cpu_mmu_index(env, false); intptr_t split, reg_off, mem_off; void *host; =20 @@ -4620,7 +4624,7 @@ static void sve_ldff1_r(CPUARMState *env, void *vg, c= onst target_ulong addr, /* Perform one normal read, which will fault or not. * But it is likely to bring the page into the tlb. */ - tlb_fn(env, vd, reg_off, addr + mem_off, mmu_idx, retaddr); + tlb_fn(env, vd, reg_off, addr + mem_off, oi, retaddr); =20 /* After any fault, zero any leading predicated false elts. */ swap_memzero(vd, reg_off); @@ -4649,7 +4653,8 @@ static void sve_ldnf1_r(CPUARMState *env, void *vg, c= onst target_ulong addr, uint32_t desc, const int esz, const int msz, sve_ld1_host_fn *host_fn) { - void *vd =3D &env->vfp.zregs[simd_data(desc)]; + const unsigned rd =3D extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT= , 5); + void *vd =3D &env->vfp.zregs[rd]; const int diffsz =3D esz - msz; const intptr_t reg_max =3D simd_oprsz(desc); const intptr_t mem_max =3D reg_max >> diffsz; @@ -4781,15 +4786,14 @@ DO_LDFF1_LDNF1_2(dd, 3, 3) #ifdef CONFIG_SOFTMMU #define DO_ST_TLB(NAME, H, TYPEM, HOST, MOEND, TLB) \ static void sve_##NAME##_tlb(CPUARMState *env, void *vd, intptr_t reg_off,= \ - target_ulong addr, int mmu_idx, uintptr_t ra)= \ + target_ulong addr, TCGMemOpIdx oi, uintptr_t = ra) \ { = \ - TCGMemOpIdx oi =3D make_memop_idx(ctz32(sizeof(TYPEM)) | MOEND, mmu_id= x); \ TLB(env, addr, *(TYPEM *)(vd + H(reg_off)), oi, ra); = \ } #else #define DO_ST_TLB(NAME, H, TYPEM, HOST, MOEND, TLB) \ static void sve_##NAME##_tlb(CPUARMState *env, void *vd, intptr_t reg_off,= \ - target_ulong addr, int mmu_idx, uintptr_t ra)= \ + target_ulong addr, TCGMemOpIdx oi, uintptr_t = ra) \ { = \ HOST(g2h(addr), *(TYPEM *)(vd + H(reg_off))); = \ } @@ -4828,9 +4832,9 @@ static void sve_st1_r(CPUARMState *env, void *vg, tar= get_ulong addr, const int esize, const int msize, sve_st1_tlb_fn *tlb_fn) { - const int mmu_idx =3D cpu_mmu_index(env, false); + const TCGMemOpIdx oi =3D extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHI= FT); + const unsigned rd =3D extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT= , 5); intptr_t i, oprsz =3D simd_oprsz(desc); - unsigned rd =3D simd_data(desc); void *vd =3D &env->vfp.zregs[rd]; =20 set_helper_retaddr(ra); @@ -4838,7 +4842,7 @@ static void sve_st1_r(CPUARMState *env, void *vg, tar= get_ulong addr, uint16_t pg =3D *(uint16_t *)(vg + H1_2(i >> 3)); do { if (pg & 1) { - tlb_fn(env, vd, i, addr, mmu_idx, ra); + tlb_fn(env, vd, i, addr, oi, ra); } i +=3D esize, pg >>=3D esize; addr +=3D msize; @@ -4852,9 +4856,9 @@ static void sve_st2_r(CPUARMState *env, void *vg, tar= get_ulong addr, const int esize, const int msize, sve_st1_tlb_fn *tlb_fn) { - const int mmu_idx =3D cpu_mmu_index(env, false); + const TCGMemOpIdx oi =3D extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHI= FT); + const unsigned rd =3D extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT= , 5); intptr_t i, oprsz =3D simd_oprsz(desc); - unsigned rd =3D simd_data(desc); void *d1 =3D &env->vfp.zregs[rd]; void *d2 =3D &env->vfp.zregs[(rd + 1) & 31]; =20 @@ -4863,8 +4867,8 @@ static void sve_st2_r(CPUARMState *env, void *vg, tar= get_ulong addr, uint16_t pg =3D *(uint16_t *)(vg + H1_2(i >> 3)); do { if (pg & 1) { - tlb_fn(env, d1, i, addr, mmu_idx, ra); - tlb_fn(env, d2, i, addr + msize, mmu_idx, ra); + tlb_fn(env, d1, i, addr, oi, ra); + tlb_fn(env, d2, i, addr + msize, oi, ra); } i +=3D esize, pg >>=3D esize; addr +=3D 2 * msize; @@ -4878,9 +4882,9 @@ static void sve_st3_r(CPUARMState *env, void *vg, tar= get_ulong addr, const int esize, const int msize, sve_st1_tlb_fn *tlb_fn) { - const int mmu_idx =3D cpu_mmu_index(env, false); + const TCGMemOpIdx oi =3D extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHI= FT); + const unsigned rd =3D extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT= , 5); intptr_t i, oprsz =3D simd_oprsz(desc); - unsigned rd =3D simd_data(desc); void *d1 =3D &env->vfp.zregs[rd]; void *d2 =3D &env->vfp.zregs[(rd + 1) & 31]; void *d3 =3D &env->vfp.zregs[(rd + 2) & 31]; @@ -4890,9 +4894,9 @@ static void sve_st3_r(CPUARMState *env, void *vg, tar= get_ulong addr, uint16_t pg =3D *(uint16_t *)(vg + H1_2(i >> 3)); do { if (pg & 1) { - tlb_fn(env, d1, i, addr, mmu_idx, ra); - tlb_fn(env, d2, i, addr + msize, mmu_idx, ra); - tlb_fn(env, d3, i, addr + 2 * msize, mmu_idx, ra); + tlb_fn(env, d1, i, addr, oi, ra); + tlb_fn(env, d2, i, addr + msize, oi, ra); + tlb_fn(env, d3, i, addr + 2 * msize, oi, ra); } i +=3D esize, pg >>=3D esize; addr +=3D 3 * msize; @@ -4906,9 +4910,9 @@ static void sve_st4_r(CPUARMState *env, void *vg, tar= get_ulong addr, const int esize, const int msize, sve_st1_tlb_fn *tlb_fn) { - const int mmu_idx =3D cpu_mmu_index(env, false); + const TCGMemOpIdx oi =3D extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHI= FT); + const unsigned rd =3D extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT= , 5); intptr_t i, oprsz =3D simd_oprsz(desc); - unsigned rd =3D simd_data(desc); void *d1 =3D &env->vfp.zregs[rd]; void *d2 =3D &env->vfp.zregs[(rd + 1) & 31]; void *d3 =3D &env->vfp.zregs[(rd + 2) & 31]; @@ -4919,10 +4923,10 @@ static void sve_st4_r(CPUARMState *env, void *vg, t= arget_ulong addr, uint16_t pg =3D *(uint16_t *)(vg + H1_2(i >> 3)); do { if (pg & 1) { - tlb_fn(env, d1, i, addr, mmu_idx, ra); - tlb_fn(env, d2, i, addr + msize, mmu_idx, ra); - tlb_fn(env, d3, i, addr + 2 * msize, mmu_idx, ra); - tlb_fn(env, d4, i, addr + 3 * msize, mmu_idx, ra); + tlb_fn(env, d1, i, addr, oi, ra); + tlb_fn(env, d2, i, addr + msize, oi, ra); + tlb_fn(env, d3, i, addr + 2 * msize, oi, ra); + tlb_fn(env, d4, i, addr + 3 * msize, oi, ra); } i +=3D esize, pg >>=3D esize; addr +=3D 4 * msize; @@ -5015,9 +5019,9 @@ static void sve_ld1_zs(CPUARMState *env, void *vd, vo= id *vg, void *vm, target_ulong base, uint32_t desc, uintptr_t ra, zreg_off_fn *off_fn, sve_ld1_tlb_fn *tlb_fn) { - const int mmu_idx =3D cpu_mmu_index(env, false); + const TCGMemOpIdx oi =3D extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHI= FT); + const int scale =3D extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, = 2); intptr_t i, oprsz =3D simd_oprsz(desc); - unsigned scale =3D simd_data(desc); ARMVectorReg scratch =3D { }; =20 set_helper_retaddr(ra); @@ -5026,7 +5030,7 @@ static void sve_ld1_zs(CPUARMState *env, void *vd, vo= id *vg, void *vm, do { if (pg & 1) { target_ulong off =3D off_fn(vm, i); - tlb_fn(env, &scratch, i, base + (off << scale), mmu_idx, r= a); + tlb_fn(env, &scratch, i, base + (off << scale), oi, ra); } i +=3D 4, pg >>=3D 4; } while (i & 15); @@ -5041,9 +5045,9 @@ static void sve_ld1_zd(CPUARMState *env, void *vd, vo= id *vg, void *vm, target_ulong base, uint32_t desc, uintptr_t ra, zreg_off_fn *off_fn, sve_ld1_tlb_fn *tlb_fn) { - const int mmu_idx =3D cpu_mmu_index(env, false); + const TCGMemOpIdx oi =3D extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHI= FT); + const int scale =3D extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, = 2); intptr_t i, oprsz =3D simd_oprsz(desc) / 8; - unsigned scale =3D simd_data(desc); ARMVectorReg scratch =3D { }; =20 set_helper_retaddr(ra); @@ -5051,7 +5055,7 @@ static void sve_ld1_zd(CPUARMState *env, void *vd, vo= id *vg, void *vm, uint8_t pg =3D *(uint8_t *)(vg + H1(i)); if (pg & 1) { target_ulong off =3D off_fn(vm, i * 8); - tlb_fn(env, &scratch, i * 8, base + (off << scale), mmu_idx, r= a); + tlb_fn(env, &scratch, i * 8, base + (off << scale), oi, ra); } } set_helper_retaddr(0); @@ -5157,7 +5161,7 @@ typedef bool sve_ld1_nf_fn(CPUARMState *env, void *vd= , intptr_t reg_off, #ifdef CONFIG_SOFTMMU #define DO_LD_NF(NAME, H, TYPEE, TYPEM, HOST) \ static bool sve_ld##NAME##_nf(CPUARMState *env, void *vd, intptr_t reg_off= , \ - target_ulong addr, int mmu_idx) = \ + target_ulong addr, int mmu_idx) = \ { = \ target_ulong next_page =3D -(addr | TARGET_PAGE_MASK); = \ if (likely(next_page - addr >=3D sizeof(TYPEM))) { = \ @@ -5216,9 +5220,10 @@ static inline void sve_ldff1_zs(CPUARMState *env, vo= id *vd, void *vg, void *vm, zreg_off_fn *off_fn, sve_ld1_tlb_fn *tlb_f= n, sve_ld1_nf_fn *nonfault_fn) { - const int mmu_idx =3D cpu_mmu_index(env, false); + const TCGMemOpIdx oi =3D extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHI= FT); + const int mmu_idx =3D get_mmuidx(oi); + const int scale =3D extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, = 2); intptr_t reg_off, reg_max =3D simd_oprsz(desc); - unsigned scale =3D simd_data(desc); target_ulong addr; =20 /* Skip to the first true predicate. */ @@ -5228,7 +5233,7 @@ static inline void sve_ldff1_zs(CPUARMState *env, voi= d *vd, void *vg, void *vm, set_helper_retaddr(ra); addr =3D off_fn(vm, reg_off); addr =3D base + (addr << scale); - tlb_fn(env, vd, reg_off, addr, mmu_idx, ra); + tlb_fn(env, vd, reg_off, addr, oi, ra); =20 /* The rest of the reads will be non-faulting. */ set_helper_retaddr(0); @@ -5257,9 +5262,10 @@ static inline void sve_ldff1_zd(CPUARMState *env, vo= id *vd, void *vg, void *vm, zreg_off_fn *off_fn, sve_ld1_tlb_fn *tlb_f= n, sve_ld1_nf_fn *nonfault_fn) { - const int mmu_idx =3D cpu_mmu_index(env, false); + const TCGMemOpIdx oi =3D extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHI= FT); + const int mmu_idx =3D get_mmuidx(oi); + const int scale =3D extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, = 2); intptr_t reg_off, reg_max =3D simd_oprsz(desc); - unsigned scale =3D simd_data(desc); target_ulong addr; =20 /* Skip to the first true predicate. */ @@ -5269,7 +5275,7 @@ static inline void sve_ldff1_zd(CPUARMState *env, voi= d *vd, void *vg, void *vm, set_helper_retaddr(ra); addr =3D off_fn(vm, reg_off); addr =3D base + (addr << scale); - tlb_fn(env, vd, reg_off, addr, mmu_idx, ra); + tlb_fn(env, vd, reg_off, addr, oi, ra); =20 /* The rest of the reads will be non-faulting. */ set_helper_retaddr(0); @@ -5381,9 +5387,9 @@ static void sve_st1_zs(CPUARMState *env, void *vd, vo= id *vg, void *vm, target_ulong base, uint32_t desc, uintptr_t ra, zreg_off_fn *off_fn, sve_ld1_tlb_fn *tlb_fn) { - const int mmu_idx =3D cpu_mmu_index(env, false); + const TCGMemOpIdx oi =3D extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHI= FT); + const int scale =3D extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, = 2); intptr_t i, oprsz =3D simd_oprsz(desc); - unsigned scale =3D simd_data(desc); =20 set_helper_retaddr(ra); for (i =3D 0; i < oprsz; ) { @@ -5391,7 +5397,7 @@ static void sve_st1_zs(CPUARMState *env, void *vd, vo= id *vg, void *vm, do { if (pg & 1) { target_ulong off =3D off_fn(vm, i); - tlb_fn(env, vd, i, base + (off << scale), mmu_idx, ra); + tlb_fn(env, vd, i, base + (off << scale), oi, ra); } i +=3D 4, pg >>=3D 4; } while (i & 15); @@ -5403,16 +5409,16 @@ static void sve_st1_zd(CPUARMState *env, void *vd, = void *vg, void *vm, target_ulong base, uint32_t desc, uintptr_t ra, zreg_off_fn *off_fn, sve_ld1_tlb_fn *tlb_fn) { - const int mmu_idx =3D cpu_mmu_index(env, false); + const TCGMemOpIdx oi =3D extract32(desc, SIMD_DATA_SHIFT, MEMOPIDX_SHI= FT); + const int scale =3D extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, = 2); intptr_t i, oprsz =3D simd_oprsz(desc) / 8; - unsigned scale =3D simd_data(desc); =20 set_helper_retaddr(ra); for (i =3D 0; i < oprsz; i++) { uint8_t pg =3D *(uint8_t *)(vg + H1(i)); if (pg & 1) { target_ulong off =3D off_fn(vm, i * 8); - tlb_fn(env, vd, i * 8, base + (off << scale), mmu_idx, ra); + tlb_fn(env, vd, i * 8, base + (off << scale), oi, ra); } } set_helper_retaddr(0); diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 20492e9b8b..05ba0518c8 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -4600,25 +4600,34 @@ static const uint8_t dtype_esz[16] =3D { 3, 2, 1, 3 }; =20 +static TCGMemOpIdx sve_memopidx(DisasContext *s, int dtype) +{ + return make_memop_idx(s->be_data | dtype_mop[dtype], get_mem_index(s)); +} + static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr, - gen_helper_gvec_mem *fn) + int dtype, gen_helper_gvec_mem *fn) { unsigned vsz =3D vec_full_reg_size(s); TCGv_ptr t_pg; - TCGv_i32 desc; + TCGv_i32 t_desc; + int desc; =20 /* For e.g. LD4, there are not enough arguments to pass all 4 * registers as pointers, so encode the regno into the data field. * For consistency, do this even for LD1. */ - desc =3D tcg_const_i32(simd_desc(vsz, vsz, zt)); + desc =3D sve_memopidx(s, dtype); + desc |=3D zt << MEMOPIDX_SHIFT; + desc =3D simd_desc(vsz, vsz, desc); + t_desc =3D tcg_const_i32(desc); t_pg =3D tcg_temp_new_ptr(); =20 tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, pg)); - fn(cpu_env, t_pg, addr, desc); + fn(cpu_env, t_pg, addr, t_desc); =20 tcg_temp_free_ptr(t_pg); - tcg_temp_free_i32(desc); + tcg_temp_free_i32(t_desc); } =20 static void do_ld_zpa(DisasContext *s, int zt, int pg, @@ -4681,7 +4690,7 @@ static void do_ld_zpa(DisasContext *s, int zt, int pg, * accessible via the instruction encoding. */ assert(fn !=3D NULL); - do_mem_zpa(s, zt, pg, addr, fn); + do_mem_zpa(s, zt, pg, addr, dtype, fn); } =20 static bool trans_LD_zprr(DisasContext *s, arg_rprr_load *a, uint32_t insn) @@ -4763,7 +4772,8 @@ static bool trans_LDFF1_zprr(DisasContext *s, arg_rpr= r_load *a, uint32_t insn) TCGv_i64 addr =3D new_tmp_a64(s); tcg_gen_shli_i64(addr, cpu_reg(s, a->rm), dtype_msz(a->dtype)); tcg_gen_add_i64(addr, addr, cpu_reg_sp(s, a->rn)); - do_mem_zpa(s, a->rd, a->pg, addr, fns[s->be_data =3D=3D MO_BE][a->= dtype]); + do_mem_zpa(s, a->rd, a->pg, addr, a->dtype, + fns[s->be_data =3D=3D MO_BE][a->dtype]); } return true; } @@ -4821,7 +4831,8 @@ static bool trans_LDNF1_zpri(DisasContext *s, arg_rpr= i_load *a, uint32_t insn) TCGv_i64 addr =3D new_tmp_a64(s); =20 tcg_gen_addi_i64(addr, cpu_reg_sp(s, a->rn), off); - do_mem_zpa(s, a->rd, a->pg, addr, fns[s->be_data =3D=3D MO_BE][a->= dtype]); + do_mem_zpa(s, a->rd, a->pg, addr, a->dtype, + fns[s->be_data =3D=3D MO_BE][a->dtype]); } return true; } @@ -4836,11 +4847,14 @@ static void do_ldrq(DisasContext *s, int zt, int pg= , TCGv_i64 addr, int msz) }; unsigned vsz =3D vec_full_reg_size(s); TCGv_ptr t_pg; - TCGv_i32 desc; - int poff; + TCGv_i32 t_desc; + int desc, poff; =20 /* Load the first quadword using the normal predicated load helpers. = */ - desc =3D tcg_const_i32(simd_desc(16, 16, zt)); + desc =3D sve_memopidx(s, msz_dtype(msz)); + desc |=3D zt << MEMOPIDX_SHIFT; + desc =3D simd_desc(16, 16, desc); + t_desc =3D tcg_const_i32(desc); =20 poff =3D pred_full_reg_offset(s, pg); if (vsz > 16) { @@ -4864,10 +4878,10 @@ static void do_ldrq(DisasContext *s, int zt, int pg= , TCGv_i64 addr, int msz) t_pg =3D tcg_temp_new_ptr(); tcg_gen_addi_ptr(t_pg, cpu_env, poff); =20 - fns[s->be_data =3D=3D MO_BE][msz](cpu_env, t_pg, addr, desc); + fns[s->be_data =3D=3D MO_BE][msz](cpu_env, t_pg, addr, t_desc); =20 tcg_temp_free_ptr(t_pg); - tcg_temp_free_i32(desc); + tcg_temp_free_i32(t_desc); =20 /* Replicate that first quadword. */ if (vsz > 16) { @@ -5019,7 +5033,7 @@ static void do_st_zpa(DisasContext *s, int zt, int pg= , TCGv_i64 addr, fn =3D fn_multiple[be][nreg - 1][msz]; } assert(fn !=3D NULL); - do_mem_zpa(s, zt, pg, addr, fn); + do_mem_zpa(s, zt, pg, addr, msz_dtype(msz), fn); } =20 static bool trans_ST_zprr(DisasContext *s, arg_rprr_store *a, uint32_t ins= n) @@ -5057,24 +5071,31 @@ static bool trans_ST_zpri(DisasContext *s, arg_rpri= _store *a, uint32_t insn) *** SVE gather loads / scatter stores */ =20 -static void do_mem_zpz(DisasContext *s, int zt, int pg, int zm, int scale, - TCGv_i64 scalar, gen_helper_gvec_mem_scatter *fn) +static void do_mem_zpz(DisasContext *s, int zt, int pg, int zm, + int scale, TCGv_i64 scalar, int msz, + gen_helper_gvec_mem_scatter *fn) { unsigned vsz =3D vec_full_reg_size(s); - TCGv_i32 desc =3D tcg_const_i32(simd_desc(vsz, vsz, scale)); TCGv_ptr t_zm =3D tcg_temp_new_ptr(); TCGv_ptr t_pg =3D tcg_temp_new_ptr(); TCGv_ptr t_zt =3D tcg_temp_new_ptr(); + TCGv_i32 t_desc; + int desc; + + desc =3D sve_memopidx(s, msz_dtype(msz)); + desc |=3D scale << MEMOPIDX_SHIFT; + desc =3D simd_desc(vsz, vsz, desc); + t_desc =3D tcg_const_i32(desc); =20 tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, pg)); tcg_gen_addi_ptr(t_zm, cpu_env, vec_full_reg_offset(s, zm)); tcg_gen_addi_ptr(t_zt, cpu_env, vec_full_reg_offset(s, zt)); - fn(cpu_env, t_zt, t_pg, t_zm, scalar, desc); + fn(cpu_env, t_zt, t_pg, t_zm, scalar, t_desc); =20 tcg_temp_free_ptr(t_zt); tcg_temp_free_ptr(t_zm); tcg_temp_free_ptr(t_pg); - tcg_temp_free_i32(desc); + tcg_temp_free_i32(t_desc); } =20 /* Indexed by [be][ff][xs][u][msz]. */ @@ -5263,7 +5284,7 @@ static bool trans_LD1_zprz(DisasContext *s, arg_LD1_z= prz *a, uint32_t insn) assert(fn !=3D NULL); =20 do_mem_zpz(s, a->rd, a->pg, a->rm, a->scale * a->msz, - cpu_reg_sp(s, a->rn), fn); + cpu_reg_sp(s, a->rn), a->msz, fn); return true; } =20 @@ -5294,7 +5315,7 @@ static bool trans_LD1_zpiz(DisasContext *s, arg_LD1_z= piz *a, uint32_t insn) * by loading the immediate into the scalar parameter. */ imm =3D tcg_const_i64(a->imm << a->msz); - do_mem_zpz(s, a->rd, a->pg, a->rn, 0, imm, fn); + do_mem_zpz(s, a->rd, a->pg, a->rn, 0, imm, a->msz, fn); tcg_temp_free_i64(imm); return true; } @@ -5369,7 +5390,7 @@ static bool trans_ST1_zprz(DisasContext *s, arg_ST1_z= prz *a, uint32_t insn) g_assert_not_reached(); } do_mem_zpz(s, a->rd, a->pg, a->rm, a->scale * a->msz, - cpu_reg_sp(s, a->rn), fn); + cpu_reg_sp(s, a->rn), a->msz, fn); return true; } =20 @@ -5400,7 +5421,7 @@ static bool trans_ST1_zpiz(DisasContext *s, arg_ST1_z= piz *a, uint32_t insn) * by loading the immediate into the scalar parameter. */ imm =3D tcg_const_i64(a->imm << a->msz); - do_mem_zpz(s, a->rd, a->pg, a->rn, 0, imm, fn); + do_mem_zpz(s, a->rd, a->pg, a->rn, 0, imm, a->msz, fn); tcg_temp_free_i64(imm); return true; } --=20 2.17.1