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[97.113.8.179]) by smtp.gmail.com with ESMTPSA id m30-v6sm7355799pff.121.2018.08.08.21.22.08 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 08 Aug 2018 21:22:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=mhyzR8Zi3Rp/BTnv7kPW11xxhgksRqlAPA2BPWvADYw=; b=fIF0bqpDFVPskLNwzauX8/faeSLwEVcQH3ZBDNxRZrsIj8wJohhzJ1lg1ljcCewTwI 1emE/bfdHs4nnGIXi2jboOHjLhfw9x1S1cbiRHbUOwqdAoDTuicigKfBEvbcCqNVRUXy 3LAA2nYhXQmGW5icuNdmLyU+ULurspIwo8oWo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=mhyzR8Zi3Rp/BTnv7kPW11xxhgksRqlAPA2BPWvADYw=; b=cPYouqwux++YO5f0pYN0RrESUmdCiubaMIQ0iXunE/sG+vNmPhj9T28M13L0HymKPo ALaNSnZoT23g22ta5tX9wfpt5a6iJ30A+WMFy8qowhqjbgTaNZH8VzLzmEJ3q30VvIvw Rm+p2KSjSAdTUSb6hG4mi2bkOIdw3LUBk9lUseEmz81W2lb6dSNnIGIFWWQZ471WDyQn E/ByoyguPh5DNn5jdBkvTYKqaR3kJhjZ2AOxECmsPFrwMttE9+j0BSgcgRnZVqnGO8M/ EsVSU3A5Dk7vgDg+Sq4dO1VlBghQ1hnJys7NGLEyE7xAR1fbldtzxNvqMrXH8hyPJo+C 7nJw== X-Gm-Message-State: AOUpUlE+rNONkjtx+tgCNyBOC+I1QcDWP0TFORzO7t8li/LMZU/mVJDW a+gF8SY/C2b+7w+3JiQA55VKQm/EgW0= X-Google-Smtp-Source: AA+uWPwqbGD6VskU/dvmwmYkzw5ggplx4FSFgHPBQH/BErgwi5W0WHWKXh8f5vVDJ0Y4vBHrdDiZjg== X-Received: by 2002:a17:902:b784:: with SMTP id e4-v6mr503387pls.185.1533788529963; Wed, 08 Aug 2018 21:22:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 8 Aug 2018 21:21:47 -0700 Message-Id: <20180809042206.15726-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180809042206.15726-1-richard.henderson@linaro.org> References: <20180809042206.15726-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::22d Subject: [Qemu-devel] [PATCH 01/20] target/arm: Set ISAR bits for -cpu max X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent.desnogues@gmail.com, peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" For the supported extensions, fill in the appropriate bits in ID_ISAR5, ID_ISAR6, ID_AA64ISAR0, ID_AA64ISAR1. Signed-off-by: Richard Henderson --- target/arm/cpu.c | 24 +++++++++++++++++------- target/arm/cpu64.c | 36 ++++++++++++++++++++++++++++-------- 2 files changed, 45 insertions(+), 15 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index b25898ed4c..71daa39e86 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1802,19 +1802,29 @@ static void arm_max_initfn(Object *obj) kvm_arm_set_cpu_features_from_host(cpu); } else { cortex_a15_initfn(obj); + + set_feature(&cpu->env, ARM_FEATURE_V8_AES); + cpu->id_isar5 =3D deposit32(cpu->id_isar5, 4, 4, 2); + set_feature(&cpu->env, ARM_FEATURE_V8_SHA1); + cpu->id_isar5 =3D deposit32(cpu->id_isar5, 8, 4, 1); + set_feature(&cpu->env, ARM_FEATURE_V8_SHA256); + cpu->id_isar5 =3D deposit32(cpu->id_isar5, 12, 4, 1); + set_feature(&cpu->env, ARM_FEATURE_CRC); + cpu->id_isar5 =3D deposit32(cpu->id_isar5, 16, 4, 1); + set_feature(&cpu->env, ARM_FEATURE_V8_RDM); + cpu->id_isar5 =3D deposit32(cpu->id_isar5, 24, 4, 1); + set_feature(&cpu->env, ARM_FEATURE_V8_FCMA); + cpu->id_isar5 =3D deposit32(cpu->id_isar5, 28, 4, 1); + + set_feature(&cpu->env, ARM_FEATURE_V8_DOTPROD); + cpu->id_isar6 =3D deposit32(cpu->id_isar6, 4, 4, 1); + #ifdef CONFIG_USER_ONLY /* We don't set these in system emulation mode for the moment, * since we don't correctly set the ID registers to advertise them, */ set_feature(&cpu->env, ARM_FEATURE_V8); - set_feature(&cpu->env, ARM_FEATURE_V8_AES); - set_feature(&cpu->env, ARM_FEATURE_V8_SHA1); - set_feature(&cpu->env, ARM_FEATURE_V8_SHA256); set_feature(&cpu->env, ARM_FEATURE_V8_PMULL); - set_feature(&cpu->env, ARM_FEATURE_CRC); - set_feature(&cpu->env, ARM_FEATURE_V8_RDM); - set_feature(&cpu->env, ARM_FEATURE_V8_DOTPROD); - set_feature(&cpu->env, ARM_FEATURE_V8_FCMA); #endif } } diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 800bff780e..4d629bb99b 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -254,6 +254,34 @@ static void aarch64_max_initfn(Object *obj) kvm_arm_set_cpu_features_from_host(cpu); } else { aarch64_a57_initfn(obj); + + set_feature(&cpu->env, ARM_FEATURE_V8_SHA512); + cpu->id_aa64isar0 =3D deposit64(cpu->id_aa64isar0, 12, 4, 2); + + set_feature(&cpu->env, ARM_FEATURE_V8_ATOMICS); + cpu->id_aa64isar0 =3D deposit64(cpu->id_aa64isar0, 20, 4, 2); + + set_feature(&cpu->env, ARM_FEATURE_V8_RDM); + cpu->id_aa64isar0 =3D deposit64(cpu->id_aa64isar0, 28, 4, 1); + cpu->id_isar5 =3D deposit32(cpu->id_isar5, 24, 4, 1); + + set_feature(&cpu->env, ARM_FEATURE_V8_SHA3); + cpu->id_aa64isar0 =3D deposit64(cpu->id_aa64isar0, 32, 4, 1); + + set_feature(&cpu->env, ARM_FEATURE_V8_SM3); + cpu->id_aa64isar0 =3D deposit64(cpu->id_aa64isar0, 36, 4, 1); + + set_feature(&cpu->env, ARM_FEATURE_V8_SM4); + cpu->id_aa64isar0 =3D deposit64(cpu->id_aa64isar0, 40, 4, 1); + + set_feature(&cpu->env, ARM_FEATURE_V8_DOTPROD); + cpu->id_aa64isar0 =3D deposit64(cpu->id_aa64isar0, 44, 4, 1); + cpu->id_isar6 =3D deposit32(cpu->id_isar6, 4, 4, 1); + + set_feature(&cpu->env, ARM_FEATURE_V8_FCMA); + cpu->id_aa64isar1 =3D deposit64(cpu->id_aa64isar1, 16, 4, 1); + cpu->id_isar5 =3D deposit32(cpu->id_isar5, 28, 4, 1); + #ifdef CONFIG_USER_ONLY /* We don't set these in system emulation mode for the moment, * since we don't correctly set the ID registers to advertise them, @@ -261,15 +289,7 @@ static void aarch64_max_initfn(Object *obj) * whereas the architecture requires them to be present in both if * present in either. */ - set_feature(&cpu->env, ARM_FEATURE_V8_SHA512); - set_feature(&cpu->env, ARM_FEATURE_V8_SHA3); - set_feature(&cpu->env, ARM_FEATURE_V8_SM3); - set_feature(&cpu->env, ARM_FEATURE_V8_SM4); - set_feature(&cpu->env, ARM_FEATURE_V8_ATOMICS); - set_feature(&cpu->env, ARM_FEATURE_V8_RDM); - set_feature(&cpu->env, ARM_FEATURE_V8_DOTPROD); set_feature(&cpu->env, ARM_FEATURE_V8_FP16); - set_feature(&cpu->env, ARM_FEATURE_V8_FCMA); set_feature(&cpu->env, ARM_FEATURE_SVE); /* For usermode -cpu max we can use a larger and more efficient DCZ * blocksize since we don't have to follow what the hardware does. --=20 2.17.1