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[97.113.8.179]) by smtp.gmail.com with ESMTPSA id q78-v6sm9674103pfi.185.2018.08.08.20.40.38 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 08 Aug 2018 20:40:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Ablu58t752cnKdeomCa6I+Hum7D6ukONMk815MNMlCI=; b=Lrh8BGuolsMa5CTx9cdrZuYOYh5HPv+hp0rP/BJ7Szkfv827MktLS5Y3j5xcfjCghM oHaGa2vdHtM9eTpsyeF/eX9xbDngFdBRzipTgkOaOFFSS3hVJjV//xe7R5TfKACHzgrp rOwIME7O5yOprBYkiIZRmS3aczHXDIICGEYz0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Ablu58t752cnKdeomCa6I+Hum7D6ukONMk815MNMlCI=; b=ET1AjdJa0E6D+Au2UODpOB98AwIIRSjDOzZn51uU8++Ie6UuTVhhBPtiFg4vZAvIHl FPsr7VVa/VNDUKzWONifbWrXqyU42zO9dnYauZ+PhToZTAQPF99omwqXqtORJhQAE6Oy C4DNGlkjpH0TkQTbBQL6S/6CqMffdK8GDzhfDs6vdm6dwL19cCNsms0YyyF0E1fira7d ajiDGLMNEC6WkWlPKftkkgjFpODzuDg1r4saRzPVk/SyN29qje6R6Pa+g0mCLWHqpV2V A9Zw/toFXtKRgxDgUw2UTZVPFcAvbqFW8vlp5Q8OZaAGRsNq3g/gjTdCqoRknIVm8FBu B5mw== X-Gm-Message-State: AOUpUlHxTSEyiVp1cyTTmhgnly/rSu7WiMyI/PmY3eNGx+Y3NGp0TsUO 83gvtsp9qLgf+gCuuQ89wy0zfw6IgVU= X-Google-Smtp-Source: AA+uWPxckG3QOsLsWX7emWmvlfvercNhHe5SzAx7Yq2zmI4ZGQLvXZ+e51aadxZpczfRXE2DEbeEJw== X-Received: by 2002:a63:ea49:: with SMTP id l9-v6mr390827pgk.427.1533786040197; Wed, 08 Aug 2018 20:40:40 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 8 Aug 2018 20:40:25 -0700 Message-Id: <20180809034033.10579-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180809034033.10579-1-richard.henderson@linaro.org> References: <20180809034033.10579-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::544 Subject: [Qemu-devel] [PATCH 03/11] target/arm: Reorganize SVE WHILE X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent.desnogues@gmail.com, peter.maydell@linaro.org, alex.bennee@linaro.org, qemu-stable@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The pseudocode for this operation is an increment + compare loop, so comparing <=3D the maximum integer produces an all-true predicate. Rather than bound in both the inline code and the helper, pass the helper the number of predicate bits to set instead of the number of predicate elements to set. Cc: qemu-stable@nongnu.org (3.0.1) Tested-by: Laurent Desnogues Reviewed-by: Laurent Desnogues Reported-by: Laurent Desnogues Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- target/arm/sve_helper.c | 5 ---- target/arm/translate-sve.c | 49 +++++++++++++++++++++++++------------- 2 files changed, 32 insertions(+), 22 deletions(-) diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index 9bd0694d55..87594a8adb 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -2846,11 +2846,6 @@ uint32_t HELPER(sve_while)(void *vd, uint32_t count,= uint32_t pred_desc) return flags; } =20 - /* Scale from predicate element count to bits. */ - count <<=3D esz; - /* Bound to the bits in the predicate. */ - count =3D MIN(count, oprsz * 8); - /* Set all of the requested bits. */ for (i =3D 0; i < count / 64; ++i) { d->p[i] =3D esz_mask; diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 9dd4c38bab..89efc80ee7 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -3173,19 +3173,19 @@ static bool trans_CTERM(DisasContext *s, arg_CTERM = *a, uint32_t insn) =20 static bool trans_WHILE(DisasContext *s, arg_WHILE *a, uint32_t insn) { - if (!sve_access_check(s)) { - return true; - } - - TCGv_i64 op0 =3D read_cpu_reg(s, a->rn, 1); - TCGv_i64 op1 =3D read_cpu_reg(s, a->rm, 1); - TCGv_i64 t0 =3D tcg_temp_new_i64(); - TCGv_i64 t1 =3D tcg_temp_new_i64(); + TCGv_i64 op0, op1, t0, t1, tmax; TCGv_i32 t2, t3; TCGv_ptr ptr; unsigned desc, vsz =3D vec_full_reg_size(s); TCGCond cond; =20 + if (!sve_access_check(s)) { + return true; + } + + op0 =3D read_cpu_reg(s, a->rn, 1); + op1 =3D read_cpu_reg(s, a->rm, 1); + if (!a->sf) { if (a->u) { tcg_gen_ext32u_i64(op0, op0); @@ -3198,32 +3198,47 @@ static bool trans_WHILE(DisasContext *s, arg_WHILE = *a, uint32_t insn) =20 /* For the helper, compress the different conditions into a computation * of how many iterations for which the condition is true. - * - * This is slightly complicated by 0 <=3D UINT64_MAX, which is nominal= ly - * 2**64 iterations, overflowing to 0. Of course, predicate registers - * aren't that large, so any value >=3D predicate size is sufficient. */ + t0 =3D tcg_temp_new_i64(); + t1 =3D tcg_temp_new_i64(); tcg_gen_sub_i64(t0, op1, op0); =20 - /* t0 =3D MIN(op1 - op0, vsz). */ - tcg_gen_movi_i64(t1, vsz); - tcg_gen_umin_i64(t0, t0, t1); + tmax =3D tcg_const_i64(vsz >> a->esz); if (a->eq) { /* Equality means one more iteration. */ tcg_gen_addi_i64(t0, t0, 1); + + /* If op1 is max (un)signed integer (and the only time the addition + * above could overflow), then we produce an all-true predicate by + * setting the count to the vector length. This is because the + * pseudocode is described as an increment + compare loop, and the + * max integer would always compare true. + */ + tcg_gen_movi_i64(t1, (a->sf + ? (a->u ? UINT64_MAX : INT64_MAX) + : (a->u ? UINT32_MAX : INT32_MAX))); + tcg_gen_movcond_i64(TCG_COND_EQ, t0, op1, t1, tmax, t0); } =20 - /* t0 =3D (condition true ? t0 : 0). */ + /* Bound to the maximum. */ + tcg_gen_umin_i64(t0, t0, tmax); + tcg_temp_free_i64(tmax); + + /* Set the count to zero if the condition is false. */ cond =3D (a->u ? (a->eq ? TCG_COND_LEU : TCG_COND_LTU) : (a->eq ? TCG_COND_LE : TCG_COND_LT)); tcg_gen_movi_i64(t1, 0); tcg_gen_movcond_i64(cond, t0, op0, op1, t0, t1); + tcg_temp_free_i64(t1); =20 + /* Since we're bounded, pass as a 32-bit type. */ t2 =3D tcg_temp_new_i32(); tcg_gen_extrl_i64_i32(t2, t0); tcg_temp_free_i64(t0); - tcg_temp_free_i64(t1); + + /* Scale elements to bits. */ + tcg_gen_shli_i32(t2, t2, a->esz); =20 desc =3D (vsz / 8) - 2; desc =3D deposit32(desc, SIMD_DATA_SHIFT, 2, a->esz); --=20 2.17.1