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[97.113.8.179]) by smtp.gmail.com with ESMTPSA id q78-v6sm9674103pfi.185.2018.08.08.20.40.50 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 08 Aug 2018 20:40:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=RTV9YUpP5y3oJ9ECtxuaAeHR5syAJ7q9647bx+XF62o=; b=b0RwnkoGTdjgbT/Z1U1I/OSemma3T+1GL82Wha8HZ5ky0/efxTWIQ/r4QJJIHqHl9s CTrNbFQa0XlzIuuMj4Ol0kZI+gD7ERxSzp7CEuqeqZFhNQdfg1fKh614oEVSwmre33XS WlMjvkPIXBH8+1e9dXOuJ+x4xpni1Q+sLriMo= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=RTV9YUpP5y3oJ9ECtxuaAeHR5syAJ7q9647bx+XF62o=; b=Q/DQNpJwusnvdtg1GzvLN31aVE766q0ujRcxFVnKQaJW5HJdBCajjQHY4rM1jJurra Dgolt1yKf90ugSSyJ1FUFp7MAC1oDbWLQul79il7MhT611ehvTqw8mZ7gLVTII4mzVtF ADkQKL+Pj7DRmzADvol72Nk+tEuZPgaJLroxrWEfdAwyg4XldTA+rx7k3XfvcZQVrC7o 8heBJ54zvmm9nRDYZx8wRttDbbRrk3A/L/eynLMzA3kwkLD6nZXIHyED2lJ72WAAILv5 bR6lF0oItofEG7u6h4NSKzWCXVEJ7Cj5SnliCZE65PIxvSgL8FVtKZ4yI2XupR6xy1L1 CUSQ== X-Gm-Message-State: AOUpUlGRVouuM6UxO/N2gqwihCvm4pDxVfUjYVvRbbWeNZCHcQ3GeD50 TgGH45baHG+QruZ52f+khfKVTQ6HVlY= X-Google-Smtp-Source: AA+uWPz7MpMEunC0j/09o5O9LMxRdRdAaESf+fqcTqXLciLjjedTBPT00y+YL94Tp19da3Ls2qI4MA== X-Received: by 2002:a62:7086:: with SMTP id l128-v6mr481071pfc.144.1533786051885; Wed, 08 Aug 2018 20:40:51 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 8 Aug 2018 20:40:33 -0700 Message-Id: <20180809034033.10579-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180809034033.10579-1-richard.henderson@linaro.org> References: <20180809034033.10579-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::444 Subject: [Qemu-devel] [PATCH 11/11] target/arm: Add sve-max-vq cpu property to -cpu max X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent.desnogues@gmail.com, peter.maydell@linaro.org, alex.bennee@linaro.org, qemu-stable@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This allows the default (and maximum) vector length to be set from the command-line. Which is extraordinarily helpful in debuging problems depending on vector length without having to bake knowledge of PR_SET_SVE_VL into every guest binary. Cc: qemu-stable@nongnu.org (3.0.1) Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Tested-by: Alex Benn=C3=A9e --- target/arm/cpu.h | 3 +++ linux-user/syscall.c | 19 +++++++++++++------ target/arm/cpu.c | 6 +++--- target/arm/cpu64.c | 29 +++++++++++++++++++++++++++++ target/arm/helper.c | 7 +++++-- 5 files changed, 53 insertions(+), 11 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index e310ffc29d..9526ed27cb 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -857,6 +857,9 @@ struct ARMCPU { =20 /* Used to synchronize KVM and QEMU in-kernel device levels */ uint8_t device_irq_level; + + /* Used to set the maximum vector length the cpu will support. */ + uint32_t sve_max_vq; }; =20 static inline ARMCPU *arm_env_get_cpu(CPUARMState *env) diff --git a/linux-user/syscall.c b/linux-user/syscall.c index dfc851cc35..5a4af76c03 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -10848,15 +10848,22 @@ abi_long do_syscall(void *cpu_env, int num, abi_l= ong arg1, #endif #ifdef TARGET_AARCH64 case TARGET_PR_SVE_SET_VL: - /* We cannot support either PR_SVE_SET_VL_ONEXEC - or PR_SVE_VL_INHERIT. Therefore, anything above - ARM_MAX_VQ results in EINVAL. */ + /* + * We cannot support either PR_SVE_SET_VL_ONEXEC or + * PR_SVE_VL_INHERIT. Note the kernel definition + * of sve_vl_valid allows for VQ=3D512, i.e. VL=3D8192, + * even though the current architectural maximum is VQ=3D16. + */ ret =3D -TARGET_EINVAL; if (arm_feature(cpu_env, ARM_FEATURE_SVE) - && arg2 >=3D 0 && arg2 <=3D ARM_MAX_VQ * 16 && !(arg2 & 15= )) { + && arg2 >=3D 0 && arg2 <=3D 512 * 16 && !(arg2 & 15)) { CPUARMState *env =3D cpu_env; - int old_vq =3D (env->vfp.zcr_el[1] & 0xf) + 1; - int vq =3D MAX(arg2 / 16, 1); + ARMCPU *cpu =3D arm_env_get_cpu(env); + uint32_t vq, old_vq; + + old_vq =3D (env->vfp.zcr_el[1] & 0xf) + 1; + vq =3D MAX(arg2 / 16, 1); + vq =3D MIN(vq, cpu->sve_max_vq); =20 if (vq < old_vq) { aarch64_sve_narrow_vq(env, vq); diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 64a8005a4b..b25898ed4c 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -168,9 +168,9 @@ static void arm_cpu_reset(CPUState *s) env->cp15.cpacr_el1 =3D deposit64(env->cp15.cpacr_el1, 16, 2, 3); env->cp15.cptr_el[3] |=3D CPTR_EZ; /* with maximum vector length */ - env->vfp.zcr_el[1] =3D ARM_MAX_VQ - 1; - env->vfp.zcr_el[2] =3D ARM_MAX_VQ - 1; - env->vfp.zcr_el[3] =3D ARM_MAX_VQ - 1; + env->vfp.zcr_el[1] =3D cpu->sve_max_vq - 1; + env->vfp.zcr_el[2] =3D env->vfp.zcr_el[1]; + env->vfp.zcr_el[3] =3D env->vfp.zcr_el[1]; #else /* Reset into the highest available EL */ if (arm_feature(env, ARM_FEATURE_EL3)) { diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index d0581d59d8..800bff780e 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -29,6 +29,7 @@ #include "sysemu/sysemu.h" #include "sysemu/kvm.h" #include "kvm_arm.h" +#include "qapi/visitor.h" =20 static inline void set_feature(CPUARMState *env, int feature) { @@ -217,6 +218,29 @@ static void aarch64_a53_initfn(Object *obj) define_arm_cp_regs(cpu, cortex_a57_a53_cp_reginfo); } =20 +static void cpu_max_get_sve_vq(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + visit_type_uint32(v, name, &cpu->sve_max_vq, errp); +} + +static void cpu_max_set_sve_vq(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + Error *err =3D NULL; + + visit_type_uint32(v, name, &cpu->sve_max_vq, &err); + + if (!err && (cpu->sve_max_vq =3D=3D 0 || cpu->sve_max_vq > ARM_MAX_VQ)= ) { + error_setg(&err, "unsupported SVE vector length"); + error_append_hint(&err, "Valid sve-max-vq in range [1-%d]\n", + ARM_MAX_VQ); + } + error_propagate(errp, err); +} + /* -cpu max: if KVM is enabled, like -cpu host (best possible with this ho= st); * otherwise, a CPU with as many features enabled as our emulation support= s. * The version of '-cpu max' for qemu-system-arm is defined in cpu.c; @@ -253,6 +277,10 @@ static void aarch64_max_initfn(Object *obj) cpu->ctr =3D 0x80038003; /* 32 byte I and D cacheline size, VIPT i= cache */ cpu->dcz_blocksize =3D 7; /* 512 bytes */ #endif + + cpu->sve_max_vq =3D ARM_MAX_VQ; + object_property_add(obj, "sve-max-vq", "uint32", cpu_max_get_sve_v= q, + cpu_max_set_sve_vq, NULL, NULL, &error_fatal); } } =20 @@ -405,6 +433,7 @@ void aarch64_sve_narrow_vq(CPUARMState *env, unsigned v= q) uint64_t pmask; =20 assert(vq >=3D 1 && vq <=3D ARM_MAX_VQ); + assert(vq <=3D arm_env_get_cpu(env)->sve_max_vq); =20 /* Zap the high bits of the zregs. */ for (i =3D 0; i < 32; i++) { diff --git a/target/arm/helper.c b/target/arm/helper.c index 66afb08ee0..c24c66d43e 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -12408,9 +12408,12 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target= _ulong *pc, zcr_len =3D 0; } else { int current_el =3D arm_current_el(env); + ARMCPU *cpu =3D arm_env_get_cpu(env); =20 - zcr_len =3D env->vfp.zcr_el[current_el <=3D 1 ? 1 : current_el= ]; - zcr_len &=3D 0xf; + zcr_len =3D cpu->sve_max_vq - 1; + if (current_el <=3D 1) { + zcr_len =3D MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[1= ]); + } if (current_el < 2 && arm_feature(env, ARM_FEATURE_EL2)) { zcr_len =3D MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[2= ]); } --=20 2.17.1