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X-Received-From: 2a00:1450:4864:20::441 Subject: [Qemu-devel] [RFC PATCH 2/4] target/arm: move decoder helpers into header X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-arm@nongnu.org, richard.henderson@linaro.org, Peter Maydell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 We want to re-use these helpers. Signed-off-by: Alex Benn=C3=A9e --- target/arm/decoder.h | 50 ++++++++++++++++++++++++++++++++++++++ target/arm/translate-sve.c | 50 +------------------------------------- 2 files changed, 51 insertions(+), 49 deletions(-) create mode 100644 target/arm/decoder.h diff --git a/target/arm/decoder.h b/target/arm/decoder.h new file mode 100644 index 0000000000..09a043fb2b --- /dev/null +++ b/target/arm/decoder.h @@ -0,0 +1,50 @@ +/* + * Helpers for extracting complex instruction fields. + * + * These are referenced in the .decode file and emitted by decodetree.py + */ + +/* See e.g. ASR (immediate, predicated). + * Returns -1 for unallocated encoding; diagnose later. + */ +static inline int tszimm_esz(int x) +{ + x >>=3D 3; /* discard imm3 */ + return 31 - clz32(x); +} + +static inline int tszimm_shr(int x) +{ + return (16 << tszimm_esz(x)) - x; +} + +/* See e.g. LSL (immediate, predicated). */ +static inline int tszimm_shl(int x) +{ + return x - (8 << tszimm_esz(x)); +} + +static inline int plus1(int x) +{ + return x + 1; +} + +/* The SH bit is in bit 8. Extract the low 8 and shift. */ +static inline int expand_imm_sh8s(int x) +{ + return (int8_t)x << (x & 0x100 ? 8 : 0); +} + +static inline int expand_imm_sh8u(int x) +{ + return (uint8_t)x << (x & 0x100 ? 8 : 0); +} + +/* Convert a 2-bit memory size (msz) to a 4-bit data type (dtype) + * with unsigned data. C.f. SVE Memory Contiguous Load Group. + */ +static inline int msz_dtype(int msz) +{ + static const uint8_t dtype[4] =3D { 0, 5, 10, 15 }; + return dtype[msz]; +} diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 374051cd20..e3ec5c8ec2 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -33,7 +33,7 @@ #include "trace-tcg.h" #include "translate-a64.h" #include "fpu/softfloat.h" - +#include "decoder.h" =20 typedef void GVecGen2sFn(unsigned, uint32_t, uint32_t, TCGv_i64, uint32_t, uint32_t); @@ -47,54 +47,6 @@ typedef void gen_helper_gvec_mem(TCGv_env, TCGv_ptr, TCG= v_i64, TCGv_i32); typedef void gen_helper_gvec_mem_scatter(TCGv_env, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i64, TCGv_i32); =20 -/* - * Helpers for extracting complex instruction fields. - */ - -/* See e.g. ASR (immediate, predicated). - * Returns -1 for unallocated encoding; diagnose later. - */ -static int tszimm_esz(int x) -{ - x >>=3D 3; /* discard imm3 */ - return 31 - clz32(x); -} - -static int tszimm_shr(int x) -{ - return (16 << tszimm_esz(x)) - x; -} - -/* See e.g. LSL (immediate, predicated). */ -static int tszimm_shl(int x) -{ - return x - (8 << tszimm_esz(x)); -} - -static inline int plus1(int x) -{ - return x + 1; -} - -/* The SH bit is in bit 8. Extract the low 8 and shift. */ -static inline int expand_imm_sh8s(int x) -{ - return (int8_t)x << (x & 0x100 ? 8 : 0); -} - -static inline int expand_imm_sh8u(int x) -{ - return (uint8_t)x << (x & 0x100 ? 8 : 0); -} - -/* Convert a 2-bit memory size (msz) to a 4-bit data type (dtype) - * with unsigned data. C.f. SVE Memory Contiguous Load Group. - */ -static inline int msz_dtype(int msz) -{ - static const uint8_t dtype[4] =3D { 0, 5, 10, 15 }; - return dtype[msz]; -} =20 /* * Include the generated decoder. --=20 2.17.1