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X-Received-From: 2a00:1450:4864:20::42e Subject: [Qemu-devel] [RFC PATCH 1/4] scripts/decodetree.py: add a disassembly generator (HACK!) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-arm@nongnu.org, richard.henderson@linaro.org, Eduardo Habkost , Cleber Rosa Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Given our issues with failing disassembly we could try and re-use the decode tree data to output what instruction is being decoded. This will be used if registered as a fall-back for when the "proper" disassembler fails to decode an instruction. Signed-off-by: Alex Benn=C3=A9e Acked-by: Eduardo Habkost --- scripts/decodetree.py | 52 ++++++++++++++++++++++++++++++++++++++----- 1 file changed, 46 insertions(+), 6 deletions(-) diff --git a/scripts/decodetree.py b/scripts/decodetree.py index 277f9a9bba..f4b4318c96 100755 --- a/scripts/decodetree.py +++ b/scripts/decodetree.py @@ -169,6 +169,7 @@ input_file =3D '' output_file =3D None output_fd =3D None insntype =3D 'uint32_t' +disassemble =3D False =20 re_ident =3D '[a-zA-Z][a-zA-Z0-9_]*' =20 @@ -467,6 +468,7 @@ class Pattern(General): =20 def output_code(self, i, extracted, outerbits, outermask): global translate_prefix + global disassemble ind =3D str_indent(i) arg =3D self.base.base.name output(ind, '/* line ', str(self.lineno), ' */\n') @@ -474,8 +476,34 @@ class Pattern(General): output(ind, self.base.extract_name(), '(&u.f_', arg, ', insn);= \n') for n, f in self.fields.items(): output(ind, 'u.f_', arg, '.', n, ' =3D ', f.str_extract(), ';\= n') - output(ind, 'return ', translate_prefix, '_', self.name, - '(ctx, &u.f_', arg, ', insn);\n') + output(ind, 'return ', translate_prefix, '_', self.name) + if disassemble: + output("(dstr, maxd, ") + else: + output("(ctx, ") + + output('&u.f_', arg) + + if disassemble: + output(");\n") + else: + output(', insn);\n') + + def output_formatter(self): + global translate_prefix + arg =3D self.base.base.name + output('/* line ', str(self.lineno), ' */\n') + output('typedef ', self.base.base.struct_name(), + ' arg_', self.name, ';\n') + output(translate_scope, 'bool ', translate_prefix, '_', self.name, + '(char *ptr, size_t n, arg_', self.name, ' *a)\n') + output("{\n") + output(str_indent(4), 'snprintf(ptr, n, "', self.name) + # fill in arguments here + output('"); \n') + output(str_indent(4), "return true;\n") + output("}\n") + # end Pattern =20 =20 @@ -973,11 +1001,12 @@ def main(): global insnwidth global insntype global insnmask + global disassemble =20 decode_function =3D 'decode' decode_scope =3D 'static ' =20 - long_opts =3D ['decode=3D', 'translate=3D', 'output=3D', 'insnwidth=3D= '] + long_opts =3D ['decode=3D', 'translate=3D', 'output=3D', 'insnwidth=3D= ', 'disassemble'] try: (opts, args) =3D getopt.getopt(sys.argv[1:], 'o:w:', long_opts) except getopt.GetoptError as err: @@ -998,6 +1027,8 @@ def main(): insnmask =3D 0xffff elif insnwidth !=3D 32: error(0, 'cannot handle insns of width', insnwidth) + elif o =3D=3D '--disassemble': + disassemble =3D True else: assert False, 'unhandled option' =20 @@ -1031,7 +1062,10 @@ def main(): if i.base.base !=3D p.base.base: error(0, i.name, ' has conflicting argument sets') else: - i.output_decl() + if disassemble: + i.output_formatter() + else: + i.output_decl() out_pats[i.name] =3D i output('\n') =20 @@ -1039,8 +1073,14 @@ def main(): f =3D formats[n] f.output_extract() =20 - output(decode_scope, 'bool ', decode_function, - '(DisasContext *ctx, ', insntype, ' insn)\n{\n') + output(decode_scope, 'bool ', decode_function) + + if disassemble: + output("(char *dstr, size_t maxd, ") + else: + output('(DisasContext *ctx, ') + + output(insntype, ' insn)\n{\n') =20 i4 =3D str_indent(4) output(i4, 'union {\n') --=20 2.17.1 From nobody Wed Nov 5 07:32:44 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; 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X-Received-From: 2a00:1450:4864:20::441 Subject: [Qemu-devel] [RFC PATCH 2/4] target/arm: move decoder helpers into header X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-arm@nongnu.org, richard.henderson@linaro.org, Peter Maydell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 We want to re-use these helpers. Signed-off-by: Alex Benn=C3=A9e --- target/arm/decoder.h | 50 ++++++++++++++++++++++++++++++++++++++ target/arm/translate-sve.c | 50 +------------------------------------- 2 files changed, 51 insertions(+), 49 deletions(-) create mode 100644 target/arm/decoder.h diff --git a/target/arm/decoder.h b/target/arm/decoder.h new file mode 100644 index 0000000000..09a043fb2b --- /dev/null +++ b/target/arm/decoder.h @@ -0,0 +1,50 @@ +/* + * Helpers for extracting complex instruction fields. + * + * These are referenced in the .decode file and emitted by decodetree.py + */ + +/* See e.g. ASR (immediate, predicated). + * Returns -1 for unallocated encoding; diagnose later. + */ +static inline int tszimm_esz(int x) +{ + x >>=3D 3; /* discard imm3 */ + return 31 - clz32(x); +} + +static inline int tszimm_shr(int x) +{ + return (16 << tszimm_esz(x)) - x; +} + +/* See e.g. LSL (immediate, predicated). */ +static inline int tszimm_shl(int x) +{ + return x - (8 << tszimm_esz(x)); +} + +static inline int plus1(int x) +{ + return x + 1; +} + +/* The SH bit is in bit 8. Extract the low 8 and shift. */ +static inline int expand_imm_sh8s(int x) +{ + return (int8_t)x << (x & 0x100 ? 8 : 0); +} + +static inline int expand_imm_sh8u(int x) +{ + return (uint8_t)x << (x & 0x100 ? 8 : 0); +} + +/* Convert a 2-bit memory size (msz) to a 4-bit data type (dtype) + * with unsigned data. C.f. SVE Memory Contiguous Load Group. + */ +static inline int msz_dtype(int msz) +{ + static const uint8_t dtype[4] =3D { 0, 5, 10, 15 }; + return dtype[msz]; +} diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 374051cd20..e3ec5c8ec2 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -33,7 +33,7 @@ #include "trace-tcg.h" #include "translate-a64.h" #include "fpu/softfloat.h" - +#include "decoder.h" =20 typedef void GVecGen2sFn(unsigned, uint32_t, uint32_t, TCGv_i64, uint32_t, uint32_t); @@ -47,54 +47,6 @@ typedef void gen_helper_gvec_mem(TCGv_env, TCGv_ptr, TCG= v_i64, TCGv_i32); typedef void gen_helper_gvec_mem_scatter(TCGv_env, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i64, TCGv_i32); =20 -/* - * Helpers for extracting complex instruction fields. - */ - -/* See e.g. ASR (immediate, predicated). - * Returns -1 for unallocated encoding; diagnose later. - */ -static int tszimm_esz(int x) -{ - x >>=3D 3; /* discard imm3 */ - return 31 - clz32(x); -} - -static int tszimm_shr(int x) -{ - return (16 << tszimm_esz(x)) - x; -} - -/* See e.g. LSL (immediate, predicated). */ -static int tszimm_shl(int x) -{ - return x - (8 << tszimm_esz(x)); -} - -static inline int plus1(int x) -{ - return x + 1; -} - -/* The SH bit is in bit 8. Extract the low 8 and shift. */ -static inline int expand_imm_sh8s(int x) -{ - return (int8_t)x << (x & 0x100 ? 8 : 0); -} - -static inline int expand_imm_sh8u(int x) -{ - return (uint8_t)x << (x & 0x100 ? 8 : 0); -} - -/* Convert a 2-bit memory size (msz) to a 4-bit data type (dtype) - * with unsigned data. C.f. SVE Memory Contiguous Load Group. - */ -static inline int msz_dtype(int msz) -{ - static const uint8_t dtype[4] =3D { 0, 5, 10, 15 }; - return dtype[msz]; -} =20 /* * Include the generated decoder. --=20 2.17.1 From nobody Wed Nov 5 07:32:44 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 153373359975918.047055526120403; Wed, 8 Aug 2018 06:06:39 -0700 (PDT) Received: from localhost ([::1]:43614 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fnOAg-0002Ii-Ef for importer@patchew.org; Wed, 08 Aug 2018 09:06:38 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35475) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fnNkc-0004Xg-6v for qemu-devel@nongnu.org; Wed, 08 Aug 2018 08:39:44 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fnNka-0006yu-I5 for qemu-devel@nongnu.org; Wed, 08 Aug 2018 08:39:42 -0400 Received: from mail-wr1-x444.google.com ([2a00:1450:4864:20::444]:33328) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fnNka-0006wL-5t for qemu-devel@nongnu.org; Wed, 08 Aug 2018 08:39:40 -0400 Received: by mail-wr1-x444.google.com with SMTP id g6-v6so1909805wrp.0 for ; Wed, 08 Aug 2018 05:39:40 -0700 (PDT) Received: from zen.linaro.local ([81.128.185.34]) by smtp.gmail.com with ESMTPSA id 8-v6sm9350975wmw.34.2018.08.08.05.39.34 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 08 Aug 2018 05:39:35 -0700 (PDT) Received: from zen.linaroharston (localhost [127.0.0.1]) by zen.linaro.local (Postfix) with ESMTP id 90D503E0625; Wed, 8 Aug 2018 13:39:34 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ZdYBzurg9prqy4LtY5QrG2Or37uNr2pMAaPFSDW/xqQ=; b=hnGw33Y/ONiw5MjOeQnU/dBy682+upLZ+WZdyVSx2uMxFcpVOBhxV/FiQ0YgSrIlmd aIiCc0jqVu+Qey888NzX53tTKRUJT1tex50Py7yRQLKZlm6K4N5rorMae0bmDA38h+RE 7AQmFuTfOXFfq37JGtg1JUohAvqubFNvnl7Mg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ZdYBzurg9prqy4LtY5QrG2Or37uNr2pMAaPFSDW/xqQ=; b=ejUBHZoG6tPvNhQ8w4NuLFp4u6P2+b9Q1Q+aQvOk7MNEsu9U2paduj8LxPpKnIMzpY d5NCZQ2o/8DMkpUPLztU9oNmKsKnW7igGvjloejrP/kBjLqWN6FQ7pZyVkfwWa3hcxC5 VeHLT8QQnyA1tZbLzZX/InTy8+skWUpWPB7ouyZVcu7wlg64szpXl5ctgPt7pOIdmiIq LwAOyBOcxmrFh+9UZz2zcKsUskIcg9t7gRkxhL6f1s3kle6OIfROiPUNaN6DHGtvw2/C F/8T5UdG1tw+mM1m0+2tq24kkaB3jFO/HWhDOHwFQiT2iCNG269361vxmLUpH4lIXxkJ SMGg== X-Gm-Message-State: AOUpUlF5/SXKRra2AINiO+73jB9WvuWSnMQyBhPd/kO4uEI7FMxenhwl Y5TxaeBe82+P8szMQxPFPJDz7g== X-Google-Smtp-Source: AA+uWPxiNON81tMwQse8KGznNUzAkEbmPBRLNurO6Utj/ILty1QyrHaXO9o56LfpWKDO5VGdi3de3A== X-Received: by 2002:adf:ecc6:: with SMTP id s6-v6mr1915060wro.160.1533731979071; Wed, 08 Aug 2018 05:39:39 -0700 (PDT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Date: Wed, 8 Aug 2018 13:39:33 +0100 Message-Id: <20180808123934.17450-4-alex.bennee@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180808123934.17450-1-alex.bennee@linaro.org> References: <20180808123934.17450-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 Subject: [Qemu-devel] [RFC PATCH 3/4] target/arm: add a fallback disassemble function X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-arm@nongnu.org, richard.henderson@linaro.org, Peter Maydell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 Now we can generate a disassembler we need a function to hook into it. As we only deal with SVE instructions at the moment we don't need to differentiate the various decoders. I special case 0x5af0 as it is used by RISU for checkpoints. Signed-off-by: Alex Benn=C3=A9e --- target/arm/Makefile.objs | 8 ++++++++ target/arm/disassemble.c | 22 ++++++++++++++++++++++ target/arm/internals.h | 2 ++ 3 files changed, 32 insertions(+) create mode 100644 target/arm/disassemble.c diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs index 11c7baf8a3..4339353df8 100644 --- a/target/arm/Makefile.objs +++ b/target/arm/Makefile.objs @@ -20,3 +20,11 @@ target/arm/decode-sve.inc.c: $(SRC_PATH)/target/arm/sve.= decode $(DECODETREE) =20 target/arm/translate-sve.o: target/arm/decode-sve.inc.c obj-$(TARGET_AARCH64) +=3D translate-sve.o sve_helper.o + +target/arm/disas-sve.inc.c: $(SRC_PATH)/target/arm/sve.decode $(DECODETREE) + $(call quiet-command,\ + $(PYTHON) $(DECODETREE) --disassemble -o $@ $<,\ + "GEN", $(TARGET_DIR)$@) + +target/arm/disassemble.o: target/arm/disas-sve.inc.c +obj-$(TARGET_AARCH64) +=3D disassemble.o diff --git a/target/arm/disassemble.c b/target/arm/disassemble.c new file mode 100644 index 0000000000..801f9680cb --- /dev/null +++ b/target/arm/disassemble.c @@ -0,0 +1,22 @@ +/* + * Fallback dissasembly + */ +#include "qemu/osdep.h" +#include "cpu.h" +#include "internals.h" +#include "decoder.h" + +#include "disas-sve.inc.c" + +size_t do_aarch64_fallback_disassembly(const uint8_t *insnp, char *ptr, si= ze_t n) +{ + uint32_t insn =3D ldl_p(insnp); + + if (insn =3D=3D 0x5af0) { + snprintf(ptr, n, "illegal insn (risu checkpoint?)"); + } else if (!decode(ptr, n, insn)) { + snprintf(ptr, n, "failed decode"); + } + + return 4; +} diff --git a/target/arm/internals.h b/target/arm/internals.h index dc9357766c..80796632a2 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -796,4 +796,6 @@ static inline uint32_t arm_debug_exception_fsr(CPUARMSt= ate *env) } } =20 +size_t do_aarch64_fallback_disassembly(const uint8_t *insn, char *ptr, siz= e_t n); + #endif --=20 2.17.1 From nobody Wed Nov 5 07:32:44 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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X-Received-From: 2a00:1450:400c:c09::236 Subject: [Qemu-devel] [RFC PATCH 4/4] disas: allow capstone to defer to a fallback function on failure X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , qemu-arm@nongnu.org, richard.henderson@linaro.org, Peter Maydell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDMRC_1 RDKM_2 RSF_0 Z_629925259 SPT_0 We can abuse the CS_OPT_SKIPDATA by providing a call back when capstone can't disassemble something. The passing of the string to the dump function is a little clunky but works. Signed-off-by: Alex Benn=C3=A9e --- disas.c | 30 +++++++++++++++++++++++++++++- include/disas/bfd.h | 11 ++++++++++- target/arm/cpu.c | 4 ++++ 3 files changed, 43 insertions(+), 2 deletions(-) diff --git a/disas.c b/disas.c index 5325b7e6be..dfd2c251c5 100644 --- a/disas.c +++ b/disas.c @@ -178,6 +178,20 @@ static int print_insn_od_target(bfd_vma pc, disassembl= e_info *info) to share this across calls and across host vs target disassembly. */ static __thread cs_insn *cap_insn; =20 + +/* Handle fall-back dissasembly. We don't print here but we do set + * cap_fallback_str for cap_dump_insn to used*/ +static size_t cap_disas_fallback(const uint8_t *code, size_t code_size, + size_t offset, void *user_data) +{ + disassemble_info *info =3D (disassemble_info *) user_data; + info->cap_fallback_str =3D g_malloc0(256); + size_t skip =3D info->capstone_fallback_func(code + offset, + info->cap_fallback_str, 256= ); + return skip; +} + + /* Initialize the Capstone library. */ /* ??? It would be nice to cache this. We would need one handle for the host and one for the target. For most targets we can reset specific @@ -206,6 +220,14 @@ static cs_err cap_disas_start(disassemble_info *info, = csh *handle) cs_option(*handle, CS_OPT_SYNTAX, CS_OPT_SYNTAX_ATT); } =20 + if (info->capstone_fallback_func) { + cs_opt_skipdata skipdata =3D { + .callback =3D cap_disas_fallback, + .user_data =3D info, + }; + cs_option(*handle, CS_OPT_SKIPDATA_SETUP, (size_t) &skipdata); + } + /* "Disassemble" unknown insns as ".byte W,X,Y,Z". */ cs_option(*handle, CS_OPT_SKIPDATA, CS_OPT_ON); =20 @@ -281,7 +303,13 @@ static void cap_dump_insn(disassemble_info *info, cs_i= nsn *insn) } =20 /* Print the actual instruction. */ - print(info->stream, " %-8s %s\n", insn->mnemonic, insn->op_str); + if (info->cap_fallback_str) { + print(info->stream, " %s\n", info->cap_fallback_str); + g_free(info->cap_fallback_str); + info->cap_fallback_str =3D NULL; + } else { + print(info->stream, " %-8s %s\n", insn->mnemonic, insn->op_str); + } =20 /* Dump any remaining part of the insn on subsequent lines. */ for (i =3D split; i < n; i +=3D split) { diff --git a/include/disas/bfd.h b/include/disas/bfd.h index 1f69a6e9d3..9d99bfef48 100644 --- a/include/disas/bfd.h +++ b/include/disas/bfd.h @@ -377,6 +377,12 @@ typedef struct disassemble_info { int cap_insn_unit; int cap_insn_split; =20 + /* Fallback function to disassemble things capstone can't. */ + size_t (*capstone_fallback_func) + (const uint8_t *insn, char *ptr, size_t n); + + char *cap_fallback_str; + } disassemble_info; =20 =0C @@ -491,7 +497,10 @@ int generic_symbol_at_address(bfd_vma, struct disassem= ble_info *); (INFO).bytes_per_chunk =3D 0, \ (INFO).display_endian =3D BFD_ENDIAN_UNKNOWN, \ (INFO).disassembler_options =3D NULL, \ - (INFO).insn_info_valid =3D 0 + (INFO).insn_info_valid =3D 0, \ + (INFO).capstone_fallback_func =3D NULL, \ + (INFO).cap_fallback_str =3D NULL + =20 #ifndef ATTRIBUTE_UNUSED #define ATTRIBUTE_UNUSED __attribute__((unused)) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 64a8005a4b..cfefbfb0b9 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -519,6 +519,10 @@ static void arm_disas_set_info(CPUState *cpu, disassem= ble_info *info) info->cap_arch =3D CS_ARCH_ARM64; info->cap_insn_unit =3D 4; info->cap_insn_split =3D 4; + +#if defined(TARGET_AARCH64) + info->capstone_fallback_func =3D do_aarch64_fallback_disassembly; +#endif } else { int cap_mode; if (env->thumb) { --=20 2.17.1