From nobody Wed Nov 5 08:16:08 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 153322392357898.95336227642679; Thu, 2 Aug 2018 08:32:03 -0700 (PDT) Received: from localhost ([::1]:46334 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1flFa6-0007e9-EQ for importer@patchew.org; Thu, 02 Aug 2018 11:32:02 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38606) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1flF01-0007EL-Fk for qemu-devel@nongnu.org; Thu, 02 Aug 2018 10:54:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1flF00-00031S-Kz for qemu-devel@nongnu.org; Thu, 02 Aug 2018 10:54:45 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:43906) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1flF00-00030g-De; Thu, 02 Aug 2018 10:54:44 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1flEq8-0006JQ-Qb; Thu, 02 Aug 2018 15:44:32 +0100 From: Peter Maydell To: qemu-devel@nongnu.org Date: Thu, 2 Aug 2018 15:44:29 +0100 Message-Id: <20180802144430.13870-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180802144430.13870-1-peter.maydell@linaro.org> References: <20180802144430.13870-1-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH 2/3] hw/ppc/ppc_boards: Don't use old_mmio for ref405ep_fpga X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Herv=C3=A9=20Poussineau?= , David Gibson , qemu-ppc@nongnu.org, Alexander Graf , patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RDMRC_1 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Switch the ref405ep_fpga device away from using the old_mmio MemoryRegion accessors. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/ppc/ppc405_boards.c | 60 +++++++----------------------------------- 1 file changed, 10 insertions(+), 50 deletions(-) diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c index 70111075b33..f5a9c24b6ce 100644 --- a/hw/ppc/ppc405_boards.c +++ b/hw/ppc/ppc405_boards.c @@ -66,7 +66,7 @@ struct ref405ep_fpga_t { uint8_t reg1; }; =20 -static uint32_t ref405ep_fpga_readb (void *opaque, hwaddr addr) +static uint64_t ref405ep_fpga_readb(void *opaque, hwaddr addr, unsigned si= ze) { ref405ep_fpga_t *fpga; uint32_t ret; @@ -87,8 +87,8 @@ static uint32_t ref405ep_fpga_readb (void *opaque, hwaddr= addr) return ret; } =20 -static void ref405ep_fpga_writeb (void *opaque, - hwaddr addr, uint32_t value) +static void ref405ep_fpga_writeb(void *opaque, hwaddr addr, uint64_t value, + unsigned size) { ref405ep_fpga_t *fpga; =20 @@ -105,54 +105,14 @@ static void ref405ep_fpga_writeb (void *opaque, } } =20 -static uint32_t ref405ep_fpga_readw (void *opaque, hwaddr addr) -{ - uint32_t ret; - - ret =3D ref405ep_fpga_readb(opaque, addr) << 8; - ret |=3D ref405ep_fpga_readb(opaque, addr + 1); - - return ret; -} - -static void ref405ep_fpga_writew (void *opaque, - hwaddr addr, uint32_t value) -{ - ref405ep_fpga_writeb(opaque, addr, (value >> 8) & 0xFF); - ref405ep_fpga_writeb(opaque, addr + 1, value & 0xFF); -} - -static uint32_t ref405ep_fpga_readl (void *opaque, hwaddr addr) -{ - uint32_t ret; - - ret =3D ref405ep_fpga_readb(opaque, addr) << 24; - ret |=3D ref405ep_fpga_readb(opaque, addr + 1) << 16; - ret |=3D ref405ep_fpga_readb(opaque, addr + 2) << 8; - ret |=3D ref405ep_fpga_readb(opaque, addr + 3); - - return ret; -} - -static void ref405ep_fpga_writel (void *opaque, - hwaddr addr, uint32_t value) -{ - ref405ep_fpga_writeb(opaque, addr, (value >> 24) & 0xFF); - ref405ep_fpga_writeb(opaque, addr + 1, (value >> 16) & 0xFF); - ref405ep_fpga_writeb(opaque, addr + 2, (value >> 8) & 0xFF); - ref405ep_fpga_writeb(opaque, addr + 3, value & 0xFF); -} - static const MemoryRegionOps ref405ep_fpga_ops =3D { - .old_mmio =3D { - .read =3D { - ref405ep_fpga_readb, ref405ep_fpga_readw, ref405ep_fpga_readl, - }, - .write =3D { - ref405ep_fpga_writeb, ref405ep_fpga_writew, ref405ep_fpga_writ= el, - }, - }, - .endianness =3D DEVICE_NATIVE_ENDIAN, + .read =3D ref405ep_fpga_readb, + .write =3D ref405ep_fpga_writeb, + .impl.min_access_size =3D 1, + .impl.max_access_size =3D 1, + .valid.min_access_size =3D 1, + .valid.max_access_size =3D 4, + .endianness =3D DEVICE_BIG_ENDIAN, }; =20 static void ref405ep_fpga_reset (void *opaque) --=20 2.17.1