From nobody Mon Feb 9 05:37:16 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1533011945954681.8073459731124; Mon, 30 Jul 2018 21:39:05 -0700 (PDT) Received: from localhost ([::1]:56954 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fkMR2-0006Q7-Ra for importer@patchew.org; Tue, 31 Jul 2018 00:39:00 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57387) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fkMPA-0005R8-AJ for qemu-devel@nongnu.org; Tue, 31 Jul 2018 00:37:05 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fkMP7-0004UB-7N for qemu-devel@nongnu.org; Tue, 31 Jul 2018 00:37:04 -0400 Received: from relay2.mail.vrmd.de ([81.28.224.28]:41519) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fkMP6-0004Tw-Vm; Tue, 31 Jul 2018 00:37:01 -0400 Received: from [188.103.27.207] (helo=murray.fritz.box) by relay2.mail.vrmd.de with esmtpa (Exim 4.86_2) (envelope-from ) id 1fkMP1-0002E4-I9; Tue, 31 Jul 2018 06:36:55 +0200 From: Sebastian Bauer To: mail@sebastianbauer.info Date: Tue, 31 Jul 2018 06:36:34 +0200 Message-Id: <20180731043635.9802-2-mail@sebastianbauer.info> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180731043635.9802-1-mail@sebastianbauer.info> References: <20180731043635.9802-1-mail@sebastianbauer.info> X-Relay-User: mail@sebastianbauer.info X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 81.28.224.28 Subject: [Qemu-devel] [PATCH 1/2] ppc: Allow clients of the 440 pcix bus to specify the number of interrupts X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: agraf@suse.de, qemu-ppc@nongnu.org, qemu-devel@nongnu.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This can be done by using the newly introduced num_irqs property. In particular, this change introduces a special case if num_irqs is 1 in which case any interrupt pin will be connected to the single irq. The default case is untouched (but note that the only client is the Sam460ex board for which the special case was actually created). Signed-off-by: Sebastian Bauer --- hw/ppc/ppc440_pcix.c | 28 +++++++++++++++++++++++++--- 1 file changed, 25 insertions(+), 3 deletions(-) diff --git a/hw/ppc/ppc440_pcix.c b/hw/ppc/ppc440_pcix.c index d8af04b70f..cb7d7cfd2b 100644 --- a/hw/ppc/ppc440_pcix.c +++ b/hw/ppc/ppc440_pcix.c @@ -57,6 +57,7 @@ typedef struct PPC440PCIXState { struct PLBOutMap pom[PPC440_PCIX_NR_POMS]; struct PLBInMap pim[PPC440_PCIX_NR_PIMS]; uint32_t sts; + uint16_t num_irqs; qemu_irq irq[PCI_NUM_PINS]; AddressSpace bm_as; MemoryRegion bm; @@ -423,6 +424,12 @@ static int ppc440_pcix_map_irq(PCIDevice *pci_dev, int= irq_num) return slot - 1; } =20 +/* All pins from each slot are tied the same and only board IRQ. */ +static int ppc440_pcix_map_irq_single(PCIDevice *pci_dev, int irq_num) +{ + return 0; +} + static void ppc440_pcix_set_irq(void *opaque, int irq_num, int level) { qemu_irq *pci_irqs =3D opaque; @@ -469,6 +476,7 @@ const MemoryRegionOps ppc440_pcix_host_data_ops =3D { =20 static int ppc440_pcix_initfn(SysBusDevice *dev) { + pci_map_irq_fn map_irq; PPC440PCIXState *s; PCIHostState *h; int i; @@ -476,14 +484,22 @@ static int ppc440_pcix_initfn(SysBusDevice *dev) h =3D PCI_HOST_BRIDGE(dev); s =3D PPC440_PCIX_HOST_BRIDGE(dev); =20 - for (i =3D 0; i < ARRAY_SIZE(s->irq); i++) { + if (s->num_irqs > 4) { + fprintf(stderr, "%s: Number of irqs must not exceed 4\n", __func__= ); + return -1; + } + + for (i =3D 0; i < s->num_irqs; i++) { sysbus_init_irq(dev, &s->irq[i]); } =20 memory_region_init(&s->busmem, OBJECT(dev), "pci bus memory", UINT64_M= AX); + + map_irq =3D s->num_irqs =3D=3D 1 ? + ppc440_pcix_map_irq_single : ppc440_pcix_map_irq; h->bus =3D pci_register_root_bus(DEVICE(dev), NULL, ppc440_pcix_set_ir= q, - ppc440_pcix_map_irq, s->irq, &s->busmem, - get_system_io(), PCI_DEVFN(0, 0), 4, TYPE_PCI_BUS= ); + map_irq, s->irq, &s->busmem, get_system_io(), + PCI_DEVFN(0, 0), s->num_irqs, TYPE_PCI_BUS); =20 s->dev =3D pci_create_simple(h->bus, PCI_DEVFN(0, 0), "ppc4xx-host-bri= dge"); =20 @@ -507,6 +523,11 @@ static int ppc440_pcix_initfn(SysBusDevice *dev) return 0; } =20 +static Property ppc440_pcix_properties[] =3D { + DEFINE_PROP_UINT16("num-irqs", PPC440PCIXState, num_irqs, 4), + DEFINE_PROP_END_OF_LIST(), +}; + static void ppc440_pcix_class_init(ObjectClass *klass, void *data) { SysBusDeviceClass *k =3D SYS_BUS_DEVICE_CLASS(klass); @@ -514,6 +535,7 @@ static void ppc440_pcix_class_init(ObjectClass *klass, = void *data) =20 k->init =3D ppc440_pcix_initfn; dc->reset =3D ppc440_pcix_reset; + dc->props =3D ppc440_pcix_properties; } =20 static const TypeInfo ppc440_pcix_info =3D { --=20 2.18.0 From nobody Mon Feb 9 05:37:16 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1533011947548235.8085209542545; Mon, 30 Jul 2018 21:39:07 -0700 (PDT) Received: from localhost ([::1]:56952 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fkMQw-0006Mu-I2 for importer@patchew.org; Tue, 31 Jul 2018 00:38:54 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57385) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fkMPA-0005R7-9v for qemu-devel@nongnu.org; Tue, 31 Jul 2018 00:37:05 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fkMP8-0004UX-FZ for qemu-devel@nongnu.org; Tue, 31 Jul 2018 00:37:04 -0400 Received: from relay2.mail.vrmd.de ([81.28.224.28]:55551) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fkMP8-0004Tb-9P; Tue, 31 Jul 2018 00:37:02 -0400 Received: from [188.103.27.207] (helo=murray.fritz.box) by relay2.mail.vrmd.de with esmtpa (Exim 4.86_2) (envelope-from ) id 1fkMP4-0002E4-9N; Tue, 31 Jul 2018 06:36:58 +0200 From: Sebastian Bauer To: mail@sebastianbauer.info Date: Tue, 31 Jul 2018 06:36:35 +0200 Message-Id: <20180731043635.9802-3-mail@sebastianbauer.info> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180731043635.9802-1-mail@sebastianbauer.info> References: <20180731043635.9802-1-mail@sebastianbauer.info> X-Relay-User: mail@sebastianbauer.info X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 81.28.224.28 Subject: [Qemu-devel] [PATCH 2/2] sam460ex: Create the PCI-X bus with only one interrupt X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: agraf@suse.de, qemu-ppc@nongnu.org, qemu-devel@nongnu.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This is done by unfolding the sysbus_create_varargs() call and by announcing that only a single irq is needed before connecting the irqs before the bus is initialized. This should model the design of the SAM board better, which is that all PCI interrupts are connected to a single interrupt pin, in particular that the logical level of the destination pin is an combined or of all the individual interrupt levels. Signed-off-by: Sebastian Bauer --- hw/ppc/sam460ex.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/hw/ppc/sam460ex.c b/hw/ppc/sam460ex.c index b2b22f280d..28265bcb4c 100644 --- a/hw/ppc/sam460ex.c +++ b/hw/ppc/sam460ex.c @@ -515,10 +515,16 @@ static void sam460ex_init(MachineState *machine) =20 /* PCI bus */ ppc460ex_pcie_init(env); - /* All PCI ints are connected to the same UIC pin (cf. UBoot source) */ - dev =3D sysbus_create_varargs("ppc440-pcix-host", 0xc0ec00000, - uic[1][0], uic[1][0], uic[1][0], uic[1][0], - NULL); + + /* All PCI ints of the PCI-X bus are connected to the same UIC pin (cf. + * UBoot source) so only one connection is needed. */ + dev =3D qdev_create(NULL, "ppc440-pcix-host"); + qdev_prop_set_uint16(dev, "num-irqs", 1); + sbdev =3D SYS_BUS_DEVICE(dev); + qdev_init_nofail(dev); + sysbus_mmio_map(sbdev, 0, 0xc0ec00000); + sysbus_connect_irq(sbdev, 0, uic[1][0]); + pci_bus =3D (PCIBus *)qdev_get_child_bus(dev, "pci.0"); if (!pci_bus) { error_report("couldn't create PCI controller!"); --=20 2.18.0