From nobody Wed Feb 11 03:25:57 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1532685479841555.8616311693143; Fri, 27 Jul 2018 02:57:59 -0700 (PDT) Received: from localhost ([::1]:40049 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fizVM-0005xa-0n for importer@patchew.org; Fri, 27 Jul 2018 05:57:48 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58287) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fizSi-0003nc-UV for qemu-devel@nongnu.org; Fri, 27 Jul 2018 05:55:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fizSg-0006KB-AQ for qemu-devel@nongnu.org; Fri, 27 Jul 2018 05:55:04 -0400 Received: from greensocs.com ([193.104.36.180]:47467) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fizSY-00064E-1E; Fri, 27 Jul 2018 05:54:54 -0400 Received: from localhost (localhost [127.0.0.1]) by greensocs.com (Postfix) with ESMTP id A8EB54434B9; Fri, 27 Jul 2018 11:54:45 +0200 (CEST) Received: from greensocs.com ([127.0.0.1]) by localhost (gs-01.greensocs.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id ykn9hlZdDPOx; Fri, 27 Jul 2018 11:54:44 +0200 (CEST) Received: by greensocs.com (Postfix, from userid 998) id 509D744354B; Fri, 27 Jul 2018 11:54:44 +0200 (CEST) Received: from michell-laptop.bar.greensocs.com (antfield.tima.u-ga.fr [147.171.129.253]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: luc.michel@greensocs.com) by greensocs.com (Postfix) with ESMTPSA id CFFC4400DC8; Fri, 27 Jul 2018 11:54:43 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1532685285; bh=t5FTPMLWoI8s9cEvq8oRgL4M4MPfkYWLBMKAaqpb6uo=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=rD6S/lRgkd5maIHMLfr9wi1W8R05AGL025gacAEuFfGY8mbDQoUegrUgnsmWeYr5l 2nwv/uWdnWKxstJd7LbP4Ja2FNdg8ZxtF0Wb6dMTYrcqWzJ/XAbBQUY1aphxv1hqvh ZaTKE/Mh+jDP3phpjooTyu3LhqAgRDC7+mcw/DpM= X-Virus-Scanned: amavisd-new at greensocs.com Authentication-Results: gs-01.greensocs.com (amavisd-new); dkim=pass (1024-bit key) header.d=greensocs.com header.b=IBMnOemf; dkim=pass (1024-bit key) header.d=greensocs.com header.b=IBMnOemf DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1532685284; bh=t5FTPMLWoI8s9cEvq8oRgL4M4MPfkYWLBMKAaqpb6uo=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=IBMnOemfIxID2bpmm6JVEaNxPJdPUS00HwdXhxvQ8vtX+Dfyq1iDHxeuXuwPp9w7B WOPx/rxAnc1+Mb4RHb5qNmkbCcc9YgFNThvguMBcCmN3q6+jyXPf2jG9D4uu3/7bY1 8mSYIzbPiS9T7NJzjpvYf+QJQkrS23bGw+EPRU2c= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1532685284; bh=t5FTPMLWoI8s9cEvq8oRgL4M4MPfkYWLBMKAaqpb6uo=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=IBMnOemfIxID2bpmm6JVEaNxPJdPUS00HwdXhxvQ8vtX+Dfyq1iDHxeuXuwPp9w7B WOPx/rxAnc1+Mb4RHb5qNmkbCcc9YgFNThvguMBcCmN3q6+jyXPf2jG9D4uu3/7bY1 8mSYIzbPiS9T7NJzjpvYf+QJQkrS23bGw+EPRU2c= From: Luc Michel To: qemu-devel@nongnu.org Date: Fri, 27 Jul 2018 11:54:04 +0200 Message-Id: <20180727095421.386-4-luc.michel@greensocs.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180727095421.386-1-luc.michel@greensocs.com> References: <20180727095421.386-1-luc.michel@greensocs.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 193.104.36.180 Subject: [Qemu-devel] [PATCH v5 03/20] intc/arm_gic: Remove some dead code and put some functions static X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , mark.burton@greensocs.com, saipava@xilinx.com, edgari@xilinx.com, qemu-arm@nongnu.org, Jan Kiszka , Luc Michel Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (found 2 invalid signatures) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Some functions are now only used in arm_gic.c, put them static. Some of them where only used by the NVIC implementation and are not used anymore, so remove them. Signed-off-by: Luc Michel Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Peter Maydell --- hw/intc/arm_gic.c | 23 ++--------------------- hw/intc/gic_internal.h | 4 ---- 2 files changed, 2 insertions(+), 25 deletions(-) diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index 53b749d216..b8eba6e594 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -69,11 +69,11 @@ static inline bool gic_has_groups(GICState *s) return s->revision =3D=3D 2 || s->security_extn; } =20 /* TODO: Many places that call this routine could be optimized. */ /* Update interrupt status after enabled or pending bits have been changed= . */ -void gic_update(GICState *s) +static void gic_update(GICState *s) { int best_irq; int best_prio; int irq; int irq_level, fiq_level; @@ -135,23 +135,10 @@ void gic_update(GICState *s) qemu_set_irq(s->parent_irq[cpu], irq_level); qemu_set_irq(s->parent_fiq[cpu], fiq_level); } } =20 -void gic_set_pending_private(GICState *s, int cpu, int irq) -{ - int cm =3D 1 << cpu; - - if (gic_test_pending(s, irq, cm)) { - return; - } - - DPRINTF("Set %d pending cpu %d\n", irq, cpu); - GIC_DIST_SET_PENDING(irq, cm); - gic_update(s); -} - static void gic_set_irq_11mpcore(GICState *s, int irq, int level, int cm, int target) { if (level) { GIC_DIST_SET_LEVEL(irq, cm); @@ -577,11 +564,11 @@ static void gic_deactivate_irq(GICState *s, int cpu, = int irq, MemTxAttrs attrs) } =20 GIC_DIST_CLEAR_ACTIVE(irq, cm); } =20 -void gic_complete_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs) +static void gic_complete_irq(GICState *s, int cpu, int irq, MemTxAttrs att= rs) { int cm =3D 1 << cpu; int group; =20 DPRINTF("EOI %d\n", irq); @@ -1486,16 +1473,10 @@ static const MemoryRegionOps gic_cpu_ops =3D { .read_with_attrs =3D gic_do_cpu_read, .write_with_attrs =3D gic_do_cpu_write, .endianness =3D DEVICE_NATIVE_ENDIAN, }; =20 -/* This function is used by nvic model */ -void gic_init_irqs_and_distributor(GICState *s) -{ - gic_init_irqs_and_mmio(s, gic_set_irq, gic_ops); -} - static void arm_gic_realize(DeviceState *dev, Error **errp) { /* Device instance realize function for the GIC sysbus device */ int i; GICState *s =3D ARM_GIC(dev); diff --git a/hw/intc/gic_internal.h b/hw/intc/gic_internal.h index 6f8d242904..a2075a94db 100644 --- a/hw/intc/gic_internal.h +++ b/hw/intc/gic_internal.h @@ -73,15 +73,11 @@ #define GICC_CTLR_V2_S_MASK 0x61f =20 /* The special cases for the revision property: */ #define REV_11MPCORE 0 =20 -void gic_set_pending_private(GICState *s, int cpu, int irq); uint32_t gic_acknowledge_irq(GICState *s, int cpu, MemTxAttrs attrs); -void gic_complete_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs); -void gic_update(GICState *s); -void gic_init_irqs_and_distributor(GICState *s); void gic_dist_set_priority(GICState *s, int cpu, int irq, uint8_t val, MemTxAttrs attrs); =20 static inline bool gic_test_pending(GICState *s, int irq, int cm) { --=20 2.18.0