From nobody Wed Feb 11 03:25:54 2026 Delivered-To: importer@patchew.org Received-SPF: temperror (zoho.com: Error in retrieving data from DNS) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=temperror (zoho.com: Error in retrieving data from DNS) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1532686187893593.3417281069304; Fri, 27 Jul 2018 03:09:47 -0700 (PDT) Received: from localhost ([::1]:40119 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fizgf-00078f-4U for importer@patchew.org; Fri, 27 Jul 2018 06:09:29 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58394) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fizSm-0003vW-9O for qemu-devel@nongnu.org; Fri, 27 Jul 2018 05:55:11 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fizSj-0006Oj-GO for qemu-devel@nongnu.org; Fri, 27 Jul 2018 05:55:08 -0400 Received: from greensocs.com ([193.104.36.180]:47535) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fizSZ-0006B0-Kk; Fri, 27 Jul 2018 05:54:55 -0400 Received: from localhost (localhost [127.0.0.1]) by greensocs.com (Postfix) with ESMTP id A1732443572; Fri, 27 Jul 2018 11:54:53 +0200 (CEST) Received: from greensocs.com ([127.0.0.1]) by localhost (gs-01.greensocs.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id BHXmSf6Yr7mv; Fri, 27 Jul 2018 11:54:52 +0200 (CEST) Received: by greensocs.com (Postfix, from userid 998) id 115A94434A7; Fri, 27 Jul 2018 11:54:51 +0200 (CEST) Received: from michell-laptop.bar.greensocs.com (antfield.tima.u-ga.fr [147.171.129.253]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: luc.michel@greensocs.com) by greensocs.com (Postfix) with ESMTPSA id 9FF92400DC8; Fri, 27 Jul 2018 11:54:50 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1532685293; bh=uZEKjMi5WZD5BNpHU2rDoZN/EycDavakkg6gt1G4ncg=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=5Nt/BstQM//qrzpDMhPn3Hv+GUyEKIaMQvD/SSpIzQ+ZmOJ8KOipeFZlLo0RPCbNK p4df/vzGKZrMP8KoS3rbjWpkQ7PSafYcePMbu971C1tiR3l+vQIjQMaMJwFwJyaBME a/zU0zRzjPSGX0a/Y5k71bEl+vgbjJ9D8kzGn4Q4= X-Virus-Scanned: amavisd-new at greensocs.com Authentication-Results: gs-01.greensocs.com (amavisd-new); dkim=pass (1024-bit key) header.d=greensocs.com header.b=o4AOi6QW; dkim=pass (1024-bit key) header.d=greensocs.com header.b=JOojs2vF DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1532685291; bh=uZEKjMi5WZD5BNpHU2rDoZN/EycDavakkg6gt1G4ncg=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=o4AOi6QWxrzISVlhfkMe23tIvM5TN837lDKFsFfM0+Nt0tB7q2vo0zRRloTq0gJdb T9ICQKoA/+zGt+ZJYvo8hUgJsjCw2EgoUORH6P8q+HycI0OVoyq1W5SvHhUfHWygxv DRMYjH6mbxkgp03eE2Vh2IJDq7qHXwihd/OzEibw= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1532685290; bh=uZEKjMi5WZD5BNpHU2rDoZN/EycDavakkg6gt1G4ncg=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=JOojs2vFMlGcXXJn0Hs6RTAnRHZfaQ5IbMXY+dBRRWxnN1VKcvRWPzvQkxRk3JUU2 8l5ZsR1RlskSkmM98dNP6KQw7BKRuAtVnhYo1iL5i/87LRpIE9tNIPPmGJ3mjXBt/1 D/Q4eW/izRwfSxifw2MMzchptU0kpLpFXXeMNJV0= From: Luc Michel To: qemu-devel@nongnu.org Date: Fri, 27 Jul 2018 11:54:21 +0200 Message-Id: <20180727095421.386-21-luc.michel@greensocs.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180727095421.386-1-luc.michel@greensocs.com> References: <20180727095421.386-1-luc.michel@greensocs.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 193.104.36.180 Subject: [Qemu-devel] [PATCH v5 20/20] arm/virt: Add support for GICv2 virtualization extensions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , mark.burton@greensocs.com, saipava@xilinx.com, edgari@xilinx.com, qemu-arm@nongnu.org, Jan Kiszka , Luc Michel Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (found 3 invalid signatures) X-ZohoMail: RDKM_2 RSF_6 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add support for GICv2 virtualization extensions by mapping the necessary I/O regions and connecting the maintenance IRQ lines. Declare those additions in the device tree and in the ACPI tables. Signed-off-by: Luc Michel Reviewed-by: Peter Maydell --- hw/arm/virt-acpi-build.c | 6 +++-- hw/arm/virt.c | 52 +++++++++++++++++++++++++++++++++------- include/hw/arm/virt.h | 4 +++- 3 files changed, 50 insertions(+), 12 deletions(-) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 6ea47e2588..ce31abd62c 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -657,21 +657,23 @@ build_madt(GArray *table_data, BIOSLinker *linker, Vi= rtMachineState *vms) =20 gicc->type =3D ACPI_APIC_GENERIC_CPU_INTERFACE; gicc->length =3D sizeof(*gicc); if (vms->gic_version =3D=3D 2) { gicc->base_address =3D cpu_to_le64(memmap[VIRT_GIC_CPU].base); + gicc->gich_base_address =3D cpu_to_le64(memmap[VIRT_GIC_HYP].b= ase); + gicc->gicv_base_address =3D cpu_to_le64(memmap[VIRT_GIC_VCPU].= base); } gicc->cpu_interface_number =3D cpu_to_le32(i); gicc->arm_mpidr =3D cpu_to_le64(armcpu->mp_affinity); gicc->uid =3D cpu_to_le32(i); gicc->flags =3D cpu_to_le32(ACPI_MADT_GICC_ENABLED); =20 if (arm_feature(&armcpu->env, ARM_FEATURE_PMU)) { gicc->performance_interrupt =3D cpu_to_le32(PPI(VIRTUAL_PMU_IR= Q)); } - if (vms->virt && vms->gic_version =3D=3D 3) { - gicc->vgic_interrupt =3D cpu_to_le32(PPI(ARCH_GICV3_MAINT_IRQ)= ); + if (vms->virt) { + gicc->vgic_interrupt =3D cpu_to_le32(PPI(ARCH_GIC_MAINT_IRQ)); } } =20 if (vms->gic_version =3D=3D 3) { AcpiMadtGenericTranslator *gic_its; diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 281ddcdf6e..0807be985c 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -129,10 +129,12 @@ static const MemMapEntry a15memmap[] =3D { [VIRT_CPUPERIPHS] =3D { 0x08000000, 0x00020000 }, /* GIC distributor and CPU interfaces sit inside the CPU peripheral sp= ace */ [VIRT_GIC_DIST] =3D { 0x08000000, 0x00010000 }, [VIRT_GIC_CPU] =3D { 0x08010000, 0x00010000 }, [VIRT_GIC_V2M] =3D { 0x08020000, 0x00001000 }, + [VIRT_GIC_HYP] =3D { 0x08030000, 0x00010000 }, + [VIRT_GIC_VCPU] =3D { 0x08040000, 0x00010000 }, /* The space in between here is reserved for GICv3 CPU/vCPU/HYP */ [VIRT_GIC_ITS] =3D { 0x08080000, 0x00020000 }, /* This redistributor space allows up to 2*64kB*123 CPUs */ [VIRT_GIC_REDIST] =3D { 0x080A0000, 0x00F60000 }, [VIRT_UART] =3D { 0x09000000, 0x00001000 }, @@ -438,22 +440,37 @@ static void fdt_add_gic_node(VirtMachineState *vms) 2, vms->memmap[VIRT_GIC_REDIST2].= size); } =20 if (vms->virt) { qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", - GIC_FDT_IRQ_TYPE_PPI, ARCH_GICV3_MAINT_= IRQ, + GIC_FDT_IRQ_TYPE_PPI, ARCH_GIC_MAINT_IR= Q, GIC_FDT_IRQ_FLAGS_LEVEL_HI); } } else { /* 'cortex-a15-gic' means 'GIC v2' */ qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", "arm,cortex-a15-gic"); - qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", - 2, vms->memmap[VIRT_GIC_DIST].base, - 2, vms->memmap[VIRT_GIC_DIST].size, - 2, vms->memmap[VIRT_GIC_CPU].base, - 2, vms->memmap[VIRT_GIC_CPU].size); + if (!vms->virt) { + qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", + 2, vms->memmap[VIRT_GIC_DIST].bas= e, + 2, vms->memmap[VIRT_GIC_DIST].siz= e, + 2, vms->memmap[VIRT_GIC_CPU].base, + 2, vms->memmap[VIRT_GIC_CPU].size= ); + } else { + qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", + 2, vms->memmap[VIRT_GIC_DIST].bas= e, + 2, vms->memmap[VIRT_GIC_DIST].siz= e, + 2, vms->memmap[VIRT_GIC_CPU].base, + 2, vms->memmap[VIRT_GIC_CPU].size, + 2, vms->memmap[VIRT_GIC_HYP].base, + 2, vms->memmap[VIRT_GIC_HYP].size, + 2, vms->memmap[VIRT_GIC_VCPU].bas= e, + 2, vms->memmap[VIRT_GIC_VCPU].siz= e); + qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", + GIC_FDT_IRQ_TYPE_PPI, ARCH_GIC_MAINT_IR= Q, + GIC_FDT_IRQ_FLAGS_LEVEL_HI); + } } =20 qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", vms->gic_phandle); g_free(nodename); } @@ -571,10 +588,15 @@ static void create_gic(VirtMachineState *vms, qemu_ir= q *pic) vms->memmap[VIRT_GIC_REDIST2].size / GICV3_REDIST_= SIZE; =20 qdev_prop_set_uint32(gicdev, "redist-region-count[1]", MIN(smp_cpus - redist0_count, redist1_capacity)); } + } else { + if (!kvm_irqchip_in_kernel()) { + qdev_prop_set_bit(gicdev, "has-virtualization-extensions", + vms->virt); + } } qdev_init_nofail(gicdev); gicbusdev =3D SYS_BUS_DEVICE(gicdev); sysbus_mmio_map(gicbusdev, 0, vms->memmap[VIRT_GIC_DIST].base); if (type =3D=3D 3) { @@ -582,10 +604,14 @@ static void create_gic(VirtMachineState *vms, qemu_ir= q *pic) if (nb_redist_regions =3D=3D 2) { sysbus_mmio_map(gicbusdev, 2, vms->memmap[VIRT_GIC_REDIST2].ba= se); } } else { sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_CPU].base); + if (vms->virt) { + sysbus_mmio_map(gicbusdev, 2, vms->memmap[VIRT_GIC_HYP].base); + sysbus_mmio_map(gicbusdev, 3, vms->memmap[VIRT_GIC_VCPU].base); + } } =20 /* Wire the outputs from each CPU's generic timer and the GICv3 * maintenance interrupt signal to the appropriate GIC PPI inputs, * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inpu= ts. @@ -608,13 +634,21 @@ static void create_gic(VirtMachineState *vms, qemu_ir= q *pic) qdev_connect_gpio_out(cpudev, irq, qdev_get_gpio_in(gicdev, ppibase + timer_irq[irq= ])); } =20 - qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt",= 0, - qdev_get_gpio_in(gicdev, ppibase - + ARCH_GICV3_MAINT_IR= Q)); + if (type =3D=3D 3) { + qemu_irq irq =3D qdev_get_gpio_in(gicdev, + ppibase + ARCH_GIC_MAINT_IRQ); + qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interru= pt", + 0, irq); + } else if (vms->virt) { + qemu_irq irq =3D qdev_get_gpio_in(gicdev, + ppibase + ARCH_GIC_MAINT_IRQ); + sysbus_connect_irq(gicbusdev, i + 4 * smp_cpus, irq); + } + qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, qdev_get_gpio_in(gicdev, ppibase + VIRTUAL_PMU_IRQ)); =20 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_= IRQ)); diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index 9a870ccb6a..4cc57a7ef6 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -40,11 +40,11 @@ =20 #define NUM_GICV2M_SPIS 64 #define NUM_VIRTIO_TRANSPORTS 32 #define NUM_SMMU_IRQS 4 =20 -#define ARCH_GICV3_MAINT_IRQ 9 +#define ARCH_GIC_MAINT_IRQ 9 =20 #define ARCH_TIMER_VIRT_IRQ 11 #define ARCH_TIMER_S_EL1_IRQ 13 #define ARCH_TIMER_NS_EL1_IRQ 14 #define ARCH_TIMER_NS_EL2_IRQ 10 @@ -58,10 +58,12 @@ enum { VIRT_MEM, VIRT_CPUPERIPHS, VIRT_GIC_DIST, VIRT_GIC_CPU, VIRT_GIC_V2M, + VIRT_GIC_HYP, + VIRT_GIC_VCPU, VIRT_GIC_ITS, VIRT_GIC_REDIST, VIRT_GIC_REDIST2, VIRT_SMMU, VIRT_UART, --=20 2.18.0