From nobody Wed Feb 11 03:25:54 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1532686024033477.74930388246673; Fri, 27 Jul 2018 03:07:04 -0700 (PDT) Received: from localhost ([::1]:40106 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fizeI-0005Po-Sa for importer@patchew.org; Fri, 27 Jul 2018 06:07:02 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58404) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fizSm-0003vx-G3 for qemu-devel@nongnu.org; Fri, 27 Jul 2018 05:55:11 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fizSj-0006Oo-K6 for qemu-devel@nongnu.org; Fri, 27 Jul 2018 05:55:08 -0400 Received: from greensocs.com ([193.104.36.180]:47517) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fizSZ-00068l-Cs; Fri, 27 Jul 2018 05:54:55 -0400 Received: from localhost (localhost [127.0.0.1]) by greensocs.com (Postfix) with ESMTP id 5A956443557; Fri, 27 Jul 2018 11:54:53 +0200 (CEST) Received: from greensocs.com ([127.0.0.1]) by localhost (gs-01.greensocs.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id a9VFysUyp8CO; Fri, 27 Jul 2018 11:54:52 +0200 (CEST) Received: by greensocs.com (Postfix, from userid 998) id 9D82B44B82A; Fri, 27 Jul 2018 11:54:50 +0200 (CEST) Received: from michell-laptop.bar.greensocs.com (antfield.tima.u-ga.fr [147.171.129.253]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: luc.michel@greensocs.com) by greensocs.com (Postfix) with ESMTPSA id 4A471400DC8; Fri, 27 Jul 2018 11:54:50 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1532685293; bh=O6QDoy0sN0FD36p5qvRQ8d/ZzOPZvnpLjxX+1yuYjJo=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=T1uoHYomK7n3X2heAVMY+91hUXKSeK2Q1ROxPEtK8iY1TdPDC07d9YoBYEiVkXZn1 c6T0BLQBI3nsRJnuT3qQtWsKSgx+31GMPVQi/0zfdy5EZDHcDCvJLj/K1vcNq5s530 KaCW+Z1Dx8Vg5AP4L2QQ0AoGwMByoHFwFeMpg6VY= X-Virus-Scanned: amavisd-new at greensocs.com Authentication-Results: gs-01.greensocs.com (amavisd-new); dkim=pass (1024-bit key) header.d=greensocs.com header.b=6UXUneoJ; dkim=pass (1024-bit key) header.d=greensocs.com header.b=6UXUneoJ DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1532685290; bh=O6QDoy0sN0FD36p5qvRQ8d/ZzOPZvnpLjxX+1yuYjJo=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=6UXUneoJpv2JnlBIcN3fV24YaDq+zPUQTRQb7fUiH/anQ2WQuAYxWk5UxHzYGxjwy QO4s4p/txEbsWHVJWRfyDlLC5D4HtIhxgl9YTfHug0/RMA+xHCK3TPm5uDkrX0dGaY Rnosa1fUL4x8sggIbFl01HP8XmXi3clwhSk0P+/w= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1532685290; bh=O6QDoy0sN0FD36p5qvRQ8d/ZzOPZvnpLjxX+1yuYjJo=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=6UXUneoJpv2JnlBIcN3fV24YaDq+zPUQTRQb7fUiH/anQ2WQuAYxWk5UxHzYGxjwy QO4s4p/txEbsWHVJWRfyDlLC5D4HtIhxgl9YTfHug0/RMA+xHCK3TPm5uDkrX0dGaY Rnosa1fUL4x8sggIbFl01HP8XmXi3clwhSk0P+/w= From: Luc Michel To: qemu-devel@nongnu.org Date: Fri, 27 Jul 2018 11:54:20 +0200 Message-Id: <20180727095421.386-20-luc.michel@greensocs.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180727095421.386-1-luc.michel@greensocs.com> References: <20180727095421.386-1-luc.michel@greensocs.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 193.104.36.180 Subject: [Qemu-devel] [PATCH v5 19/20] xlnx-zynqmp: Improve GIC wiring and MMIO mapping X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , mark.burton@greensocs.com, saipava@xilinx.com, edgari@xilinx.com, qemu-arm@nongnu.org, Jan Kiszka , Luc Michel Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (found 2 invalid signatures) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This commit improve the way the GIC is realized and connected in the ZynqMP SoC. The security extensions are enabled only if requested in the machine state. The same goes for the virtualization extensions. All the GIC to APU CPU(s) IRQ lines are now connected, including FIQ, vIRQ and vFIQ. The missing CPU to GIC timers IRQ connections are also added (HYP and SEC timers). The GIC maintenance IRQs are back-wired to the correct GIC PPIs. Finally, the MMIO mappings are reworked to take into account the ZynqMP specifics. The GIC (v)CPU interface is aliased 16 times: * for the first 0x1000 bytes from 0xf9010000 to 0xf901f000 * for the second 0x1000 bytes from 0xf9020000 to 0xf902f000 Mappings of the virtual interface and virtual CPU interface are mapped only when virtualization extensions are requested. The XlnxZynqMPGICRegion struct has been enhanced to be able to catch all this information. Signed-off-by: Luc Michel Reviewed-by: Edgar E. Iglesias --- hw/arm/xlnx-zynqmp.c | 92 ++++++++++++++++++++++++++++++++---- include/hw/arm/xlnx-zynqmp.h | 4 +- 2 files changed, 86 insertions(+), 10 deletions(-) diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c index 8de4868eb9..c195040350 100644 --- a/hw/arm/xlnx-zynqmp.c +++ b/hw/arm/xlnx-zynqmp.c @@ -27,16 +27,21 @@ =20 #define GIC_NUM_SPI_INTR 160 =20 #define ARM_PHYS_TIMER_PPI 30 #define ARM_VIRT_TIMER_PPI 27 +#define ARM_HYP_TIMER_PPI 26 +#define ARM_SEC_TIMER_PPI 29 +#define GIC_MAINTENANCE_PPI 25 =20 #define GEM_REVISION 0x40070106 =20 #define GIC_BASE_ADDR 0xf9000000 #define GIC_DIST_ADDR 0xf9010000 #define GIC_CPU_ADDR 0xf9020000 +#define GIC_VIFACE_ADDR 0xf9040000 +#define GIC_VCPU_ADDR 0xf9060000 =20 #define SATA_INTR 133 #define SATA_ADDR 0xFD0C0000 #define SATA_NUM_PORTS 2 =20 @@ -109,15 +114,58 @@ static const int adma_ch_intr[XLNX_ZYNQMP_NUM_ADMA_CH= ] =3D { }; =20 typedef struct XlnxZynqMPGICRegion { int region_index; uint32_t address; + uint32_t offset; + bool virt; } XlnxZynqMPGICRegion; =20 static const XlnxZynqMPGICRegion xlnx_zynqmp_gic_regions[] =3D { - { .region_index =3D 0, .address =3D GIC_DIST_ADDR, }, - { .region_index =3D 1, .address =3D GIC_CPU_ADDR, }, + /* Distributor */ + { + .region_index =3D 0, + .address =3D GIC_DIST_ADDR, + .offset =3D 0, + .virt =3D false + }, + + /* CPU interface */ + { + .region_index =3D 1, + .address =3D GIC_CPU_ADDR, + .offset =3D 0, + .virt =3D false + }, + { + .region_index =3D 1, + .address =3D GIC_CPU_ADDR + 0x10000, + .offset =3D 0x1000, + .virt =3D false + }, + + /* Virtual interface */ + { + .region_index =3D 2, + .address =3D GIC_VIFACE_ADDR, + .offset =3D 0, + .virt =3D true + }, + + /* Virtual CPU interface */ + { + .region_index =3D 3, + .address =3D GIC_VCPU_ADDR, + .offset =3D 0, + .virt =3D true + }, + { + .region_index =3D 3, + .address =3D GIC_VCPU_ADDR + 0x10000, + .offset =3D 0x1000, + .virt =3D true + }, }; =20 static inline int arm_gic_ppi_index(int cpu_nr, int ppi_index) { return GIC_NUM_SPI_INTR + cpu_nr * GIC_INTERNAL + ppi_index; @@ -279,10 +327,13 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Err= or **errp) } =20 qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", GIC_NUM_SPI_INTR + 32= ); qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2); qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", num_apus); + qdev_prop_set_bit(DEVICE(&s->gic), "has-security-extensions", s->secur= e); + qdev_prop_set_bit(DEVICE(&s->gic), + "has-virtualization-extensions", s->virt); =20 /* Realize APUs before realizing the GIC. KVM requires this. */ for (i =3D 0; i < num_apus; i++) { char *name; =20 @@ -323,38 +374,63 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Err= or **errp) =20 assert(ARRAY_SIZE(xlnx_zynqmp_gic_regions) =3D=3D XLNX_ZYNQMP_GIC_REGI= ONS); for (i =3D 0; i < XLNX_ZYNQMP_GIC_REGIONS; i++) { SysBusDevice *gic =3D SYS_BUS_DEVICE(&s->gic); const XlnxZynqMPGICRegion *r =3D &xlnx_zynqmp_gic_regions[i]; - MemoryRegion *mr =3D sysbus_mmio_get_region(gic, r->region_index); + MemoryRegion *mr; uint32_t addr =3D r->address; int j; =20 - sysbus_mmio_map(gic, r->region_index, addr); + if (r->virt && !s->virt) { + continue; + } =20 + mr =3D sysbus_mmio_get_region(gic, r->region_index); for (j =3D 0; j < XLNX_ZYNQMP_GIC_ALIASES; j++) { MemoryRegion *alias =3D &s->gic_mr[i][j]; =20 - addr +=3D XLNX_ZYNQMP_GIC_REGION_SIZE; memory_region_init_alias(alias, OBJECT(s), "zynqmp-gic-alias",= mr, - 0, XLNX_ZYNQMP_GIC_REGION_SIZE); + r->offset, XLNX_ZYNQMP_GIC_REGION_SIZ= E); memory_region_add_subregion(system_memory, addr, alias); + + addr +=3D XLNX_ZYNQMP_GIC_REGION_SIZE; } } =20 for (i =3D 0; i < num_apus; i++) { qemu_irq irq; =20 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i, qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]), ARM_CPU_IRQ)); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus, + qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]), + ARM_CPU_FIQ)); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus * 2, + qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]), + ARM_CPU_VIRQ)); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus * 3, + qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]), + ARM_CPU_VFIQ)); irq =3D qdev_get_gpio_in(DEVICE(&s->gic), arm_gic_ppi_index(i, ARM_PHYS_TIMER_PPI)); - qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), 0, irq); + qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_PHYS, irq); irq =3D qdev_get_gpio_in(DEVICE(&s->gic), arm_gic_ppi_index(i, ARM_VIRT_TIMER_PPI)); - qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), 1, irq); + qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_VIRT, irq); + irq =3D qdev_get_gpio_in(DEVICE(&s->gic), + arm_gic_ppi_index(i, ARM_HYP_TIMER_PPI)); + qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_HYP, irq); + irq =3D qdev_get_gpio_in(DEVICE(&s->gic), + arm_gic_ppi_index(i, ARM_SEC_TIMER_PPI)); + qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_SEC, irq); + + if (s->virt) { + irq =3D qdev_get_gpio_in(DEVICE(&s->gic), + arm_gic_ppi_index(i, GIC_MAINTENANCE_PP= I)); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus * 4, = irq); + } } =20 if (s->has_rpu) { info_report("The 'has_rpu' property is no longer required, to use = the " "RPUs just use -smp 6."); diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h index 82b6ec2486..98f925ab84 100644 --- a/include/hw/arm/xlnx-zynqmp.h +++ b/include/hw/arm/xlnx-zynqmp.h @@ -51,20 +51,20 @@ =20 #define XLNX_ZYNQMP_NUM_OCM_BANKS 4 #define XLNX_ZYNQMP_OCM_RAM_0_ADDRESS 0xFFFC0000 #define XLNX_ZYNQMP_OCM_RAM_SIZE 0x10000 =20 -#define XLNX_ZYNQMP_GIC_REGIONS 2 +#define XLNX_ZYNQMP_GIC_REGIONS 6 =20 /* ZynqMP maps the ARM GIC regions (GICC, GICD ...) at consecutive 64k off= sets * and under-decodes the 64k region. This mirrors the 4k regions to every = 4k * aligned address in the 64k region. To implement each GIC region needs a * number of memory region aliases. */ =20 #define XLNX_ZYNQMP_GIC_REGION_SIZE 0x1000 -#define XLNX_ZYNQMP_GIC_ALIASES (0x10000 / XLNX_ZYNQMP_GIC_REGION_SIZE= - 1) +#define XLNX_ZYNQMP_GIC_ALIASES (0x10000 / XLNX_ZYNQMP_GIC_REGION_SIZE) =20 #define XLNX_ZYNQMP_MAX_LOW_RAM_SIZE 0x80000000ull =20 #define XLNX_ZYNQMP_MAX_HIGH_RAM_SIZE 0x800000000ull #define XLNX_ZYNQMP_HIGH_RAM_START 0x800000000ull --=20 2.18.0