From nobody Wed Feb 11 03:25:54 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1532686118786701.0812782867825; Fri, 27 Jul 2018 03:08:38 -0700 (PDT) Received: from localhost ([::1]:40116 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fizfp-0006cJ-Iy for importer@patchew.org; Fri, 27 Jul 2018 06:08:37 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58406) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fizSm-0003w4-GK for qemu-devel@nongnu.org; Fri, 27 Jul 2018 05:55:11 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fizSh-0006Lw-Dl for qemu-devel@nongnu.org; Fri, 27 Jul 2018 05:55:08 -0400 Received: from greensocs.com ([193.104.36.180]:47525) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fizSZ-00069K-1M; Fri, 27 Jul 2018 05:54:55 -0400 Received: from localhost (localhost [127.0.0.1]) by greensocs.com (Postfix) with ESMTP id 8D91844A0FE; Fri, 27 Jul 2018 11:54:50 +0200 (CEST) Received: from greensocs.com ([127.0.0.1]) by localhost (gs-01.greensocs.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id cOmBRSCSPms6; Fri, 27 Jul 2018 11:54:49 +0200 (CEST) Received: by greensocs.com (Postfix, from userid 998) id 22F7E44355C; Fri, 27 Jul 2018 11:54:48 +0200 (CEST) Received: from michell-laptop.bar.greensocs.com (antfield.tima.u-ga.fr [147.171.129.253]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: luc.michel@greensocs.com) by greensocs.com (Postfix) with ESMTPSA id B2D024434A7; Fri, 27 Jul 2018 11:54:47 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1532685290; bh=WZVYUk5e9FgMbKjFEeWXbGta6Qxx+9ye+Ey0gO/42s4=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=NgmYLZF/43UUIa4qV/Oik5R8go6XvUnCceEXjjmIVF3e3vjpVX7y36aBEWGfr+nLR QI+nPrzmWXKvMb+tb9gZ9QSYWJ120vNa0qx8sItBHT+zkRya3FZmcRgO2hrhENIbeL axk1s+Nqe6MUIMBVteD+mFMOAc9PjlZijaz+YoeM= X-Virus-Scanned: amavisd-new at greensocs.com Authentication-Results: gs-01.greensocs.com (amavisd-new); dkim=pass (1024-bit key) header.d=greensocs.com header.b=VvK65OGe; dkim=pass (1024-bit key) header.d=greensocs.com header.b=qvTzLGAj DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1532685288; bh=WZVYUk5e9FgMbKjFEeWXbGta6Qxx+9ye+Ey0gO/42s4=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=VvK65OGezA1+n0/k0PfI48+tdonz1dHQBcYbxfQh9KvSnJct4lDmYzFiDl2cLZPjE sB+SAJL0GbeCNKzhGHK1Hbq8YRdnGvPvgjn0eJxhpRghvkmRdDzEo4IVSQakXoHoJu KojWoPUpJxyiAIpeN1bu6Y86SW8stwfZlIPx6MEE= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1532685287; bh=WZVYUk5e9FgMbKjFEeWXbGta6Qxx+9ye+Ey0gO/42s4=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=qvTzLGAjgVtY3Yq0x/fvwy8VJqrVXjKPmfBgGwoMQ88j5puE1Xn984j71+mZvU/zq 28vtLas1xgi8La8l5gquPLF5EPo4KJ80IH1Rl+tnMk0lauaRkiBLxaBiXqR5yF5zSV XuGUr27mnD72zpAlt67/5U8q9sds8KEIA+WR7U+k= From: Luc Michel To: qemu-devel@nongnu.org Date: Fri, 27 Jul 2018 11:54:14 +0200 Message-Id: <20180727095421.386-14-luc.michel@greensocs.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180727095421.386-1-luc.michel@greensocs.com> References: <20180727095421.386-1-luc.michel@greensocs.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 193.104.36.180 Subject: [Qemu-devel] [PATCH v5 13/20] intc/arm_gic: Implement virtualization extensions in gic_cpu_(read|write) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , mark.burton@greensocs.com, saipava@xilinx.com, edgari@xilinx.com, qemu-arm@nongnu.org, Jan Kiszka , Luc Michel Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (found 3 invalid signatures) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Implement virtualization extensions in the gic_cpu_read() and gic_cpu_write() functions. Those are the last bits missing to fully support virtualization extensions in the CPU interface path. Signed-off-by: Luc Michel Reviewed-by: Peter Maydell --- hw/intc/arm_gic.c | 20 +++++++++++++++----- 1 file changed, 15 insertions(+), 5 deletions(-) diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index 3cddf65826..0e1b23047e 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -1399,13 +1399,16 @@ static MemTxResult gic_cpu_read(GICState *s, int cp= u, int offset, } break; case 0xd0: case 0xd4: case 0xd8: case 0xdc: { int regno =3D (offset - 0xd0) / 4; + int nr_aprs =3D gic_is_vcpu(cpu) ? GIC_VIRT_NR_APRS : GIC_NR_APRS; =20 - if (regno >=3D GIC_NR_APRS || s->revision !=3D 2) { + if (regno >=3D nr_aprs || s->revision !=3D 2) { *data =3D 0; + } else if (gic_is_vcpu(cpu)) { + *data =3D s->h_apr[gic_get_vcpu_real_id(cpu)]; } else if (gic_cpu_ns_access(s, cpu, attrs)) { /* NS view of GICC_APR is the top half of GIC_NSAPR */ *data =3D gic_apr_ns_view(s, regno, cpu); } else { *data =3D s->apr[regno][cpu]; @@ -1415,11 +1418,11 @@ static MemTxResult gic_cpu_read(GICState *s, int cp= u, int offset, case 0xe0: case 0xe4: case 0xe8: case 0xec: { int regno =3D (offset - 0xe0) / 4; =20 if (regno >=3D GIC_NR_APRS || s->revision !=3D 2 || !gic_has_group= s(s) || - gic_cpu_ns_access(s, cpu, attrs)) { + gic_cpu_ns_access(s, cpu, attrs) || gic_is_vcpu(cpu)) { *data =3D 0; } else { *data =3D s->nsapr[regno][cpu]; } break; @@ -1450,11 +1453,12 @@ static MemTxResult gic_cpu_write(GICState *s, int c= pu, int offset, return MEMTX_OK; } else { s->abpr[cpu] =3D MAX(value & 0x7, GIC_MIN_ABPR); } } else { - s->bpr[cpu] =3D MAX(value & 0x7, GIC_MIN_BPR); + int min_bpr =3D gic_is_vcpu(cpu) ? GIC_VIRT_MIN_BPR : GIC_MIN_= BPR; + s->bpr[cpu] =3D MAX(value & 0x7, min_bpr); } break; case 0x10: /* End Of Interrupt */ gic_complete_irq(s, cpu, value & 0x3ff, attrs); return MEMTX_OK; @@ -1467,15 +1471,18 @@ static MemTxResult gic_cpu_write(GICState *s, int c= pu, int offset, } break; case 0xd0: case 0xd4: case 0xd8: case 0xdc: { int regno =3D (offset - 0xd0) / 4; + int nr_aprs =3D gic_is_vcpu(cpu) ? GIC_VIRT_NR_APRS : GIC_NR_APRS; =20 - if (regno >=3D GIC_NR_APRS || s->revision !=3D 2) { + if (regno >=3D nr_aprs || s->revision !=3D 2) { return MEMTX_OK; } - if (gic_cpu_ns_access(s, cpu, attrs)) { + if (gic_is_vcpu(cpu)) { + s->h_apr[gic_get_vcpu_real_id(cpu)] =3D value; + } else if (gic_cpu_ns_access(s, cpu, attrs)) { /* NS view of GICC_APR is the top half of GIC_NSAPR */ gic_apr_write_ns_view(s, regno, cpu, value); } else { s->apr[regno][cpu] =3D value; } @@ -1486,10 +1493,13 @@ static MemTxResult gic_cpu_write(GICState *s, int c= pu, int offset, int regno =3D (offset - 0xe0) / 4; =20 if (regno >=3D GIC_NR_APRS || s->revision !=3D 2) { return MEMTX_OK; } + if (gic_is_vcpu(cpu)) { + return MEMTX_OK; + } if (!gic_has_groups(s) || (gic_cpu_ns_access(s, cpu, attrs))) { return MEMTX_OK; } s->nsapr[regno][cpu] =3D value; break; --=20 2.18.0