From nobody Wed Feb 11 03:25:54 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1532685626304181.28088212744512; Fri, 27 Jul 2018 03:00:26 -0700 (PDT) Received: from localhost ([::1]:40064 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fizXt-0000LW-01 for importer@patchew.org; Fri, 27 Jul 2018 06:00:25 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58290) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fizSi-0003ng-W5 for qemu-devel@nongnu.org; Fri, 27 Jul 2018 05:55:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fizSg-0006KH-B1 for qemu-devel@nongnu.org; Fri, 27 Jul 2018 05:55:04 -0400 Received: from greensocs.com ([193.104.36.180]:47523) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fizSY-00068v-TV; Fri, 27 Jul 2018 05:54:55 -0400 Received: from localhost (localhost [127.0.0.1]) by greensocs.com (Postfix) with ESMTP id AEA4D44A0F2; Fri, 27 Jul 2018 11:54:49 +0200 (CEST) Received: from greensocs.com ([127.0.0.1]) by localhost (gs-01.greensocs.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id hB1MMotST5hW; Fri, 27 Jul 2018 11:54:48 +0200 (CEST) Received: by greensocs.com (Postfix, from userid 998) id AE6E7400DC8; Fri, 27 Jul 2018 11:54:47 +0200 (CEST) Received: from michell-laptop.bar.greensocs.com (antfield.tima.u-ga.fr [147.171.129.253]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: luc.michel@greensocs.com) by greensocs.com (Postfix) with ESMTPSA id 591264434A7; Fri, 27 Jul 2018 11:54:47 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1532685289; bh=5WV/wNLjNyQfMb2EzAtNl4rfaf6k6INk+sl6UaUVf2I=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=QUA7H0ux95QNv+t+mLigacy9aeJ+TeHszSiW5Q+7ZDeWKNbkQ6H3Z/GBwukgN0fGC h8raCqdZaIhihlAzd8Qz1TcWTeS4eaC6v5r+EcWrl+JDHhbsKak+iQOC0irBu3kTCI DA5lB0PCrmdnIIUlEK3uY2fP+7OnPcxKE4VmfCyY= X-Virus-Scanned: amavisd-new at greensocs.com Authentication-Results: gs-01.greensocs.com (amavisd-new); dkim=pass (1024-bit key) header.d=greensocs.com header.b=UzthTwPJ; dkim=pass (1024-bit key) header.d=greensocs.com header.b=UzthTwPJ DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1532685287; bh=5WV/wNLjNyQfMb2EzAtNl4rfaf6k6INk+sl6UaUVf2I=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=UzthTwPJNJQibOzESpmFNGfp+hQAVuRIHhkXYDdLItDQvTIEKe88+OWkAEUUbHiim Qn8Kx6ZDaR9vzltqBK3foiSVNPusAuwbL7LMjcL9pboAtowHM4bS8Rk4diJbOdSavZ d3Xgbygqp0jiXBSM6LxWZJPihqLpdRqZu25eMyfE= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1532685287; bh=5WV/wNLjNyQfMb2EzAtNl4rfaf6k6INk+sl6UaUVf2I=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=UzthTwPJNJQibOzESpmFNGfp+hQAVuRIHhkXYDdLItDQvTIEKe88+OWkAEUUbHiim Qn8Kx6ZDaR9vzltqBK3foiSVNPusAuwbL7LMjcL9pboAtowHM4bS8Rk4diJbOdSavZ d3Xgbygqp0jiXBSM6LxWZJPihqLpdRqZu25eMyfE= From: Luc Michel To: qemu-devel@nongnu.org Date: Fri, 27 Jul 2018 11:54:13 +0200 Message-Id: <20180727095421.386-13-luc.michel@greensocs.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180727095421.386-1-luc.michel@greensocs.com> References: <20180727095421.386-1-luc.michel@greensocs.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 193.104.36.180 Subject: [Qemu-devel] [PATCH v5 12/20] intc/arm_gic: Implement virtualization extensions in gic_(deactivate|complete_irq) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , mark.burton@greensocs.com, saipava@xilinx.com, edgari@xilinx.com, qemu-arm@nongnu.org, Jan Kiszka , Luc Michel Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (found 2 invalid signatures) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Implement virtualization extensions in the gic_deactivate_irq() and gic_complete_irq() functions. When the guest writes an invalid vIRQ to V_EOIR or V_DIR, since the GICv2 specification is not entirely clear here, we adopt the behaviour observed on real hardware: * When V_CTRL.EOIMode is false (EOI split is disabled): - In case of an invalid vIRQ write to V_EOIR: -> If some bits are set in H_APR, an invalid vIRQ write to V_EOIR triggers a priority drop, and increments V_HCR.EOICount. -> If V_APR is already cleared, nothing happen - An invalid vIRQ write to V_DIR is ignored. * When V_CTRL.EOIMode is true: - In case of an invalid vIRQ write to V_EOIR: -> If some bits are set in H_APR, an invalid vIRQ write to V_EOIR triggers a priority drop. -> If V_APR is already cleared, nothing happen - An invalid vIRQ write to V_DIR increments V_HCR.EOICount. Signed-off-by: Luc Michel --- hw/intc/arm_gic.c | 51 +++++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 47 insertions(+), 4 deletions(-) diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index d80acde989..3cddf65826 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -581,31 +581,41 @@ static bool gic_eoi_split(GICState *s, int cpu, MemTx= Attrs attrs) =20 static void gic_deactivate_irq(GICState *s, int cpu, int irq, MemTxAttrs a= ttrs) { int group; =20 - if (irq >=3D s->num_irq) { + if (irq >=3D GIC_MAXIRQ || (!gic_is_vcpu(cpu) && irq >=3D s->num_irq))= { /* * This handles two cases: * 1. If software writes the ID of a spurious interrupt [ie 1023] * to the GICC_DIR, the GIC ignores that write. * 2. If software writes the number of a non-existent interrupt * this must be a subcase of "value written is not an active inter= rupt" - * and so this is UNPREDICTABLE. We choose to ignore it. + * and so this is UNPREDICTABLE. We choose to ignore it. For vCPUs, + * all IRQs potentially exist, so this limit does not apply. */ return; } =20 - group =3D gic_has_groups(s) && gic_test_group(s, irq, cpu); - if (!gic_eoi_split(s, cpu, attrs)) { /* This is UNPREDICTABLE; we choose to ignore it */ qemu_log_mask(LOG_GUEST_ERROR, "gic_deactivate_irq: GICC_DIR write when EOIMode cle= ar"); return; } =20 + if (gic_is_vcpu(cpu) && !gic_virq_is_valid(s, irq, cpu)) { + /* This vIRQ does not have an LR entry which is either active or + * pending and active. Increment EOICount and ignore the write. + */ + int rcpu =3D gic_get_vcpu_real_id(cpu); + s->h_hcr[rcpu] +=3D 1 << R_GICH_HCR_EOICount_SHIFT; + return; + } + + group =3D gic_has_groups(s) && gic_test_group(s, irq, cpu); + if (gic_cpu_ns_access(s, cpu, attrs) && !group) { DPRINTF("Non-secure DI for Group0 interrupt %d ignored\n", irq); return; } =20 @@ -616,10 +626,43 @@ static void gic_complete_irq(GICState *s, int cpu, in= t irq, MemTxAttrs attrs) { int cm =3D 1 << cpu; int group; =20 DPRINTF("EOI %d\n", irq); + if (gic_is_vcpu(cpu)) { + /* The call to gic_prio_drop() will clear a bit in GICH_APR iff the + * running prio is < 0x100. + */ + bool prio_drop =3D s->running_priority[cpu] < 0x100; + + if (irq >=3D GIC_MAXIRQ) { + /* Ignore spurious interrupt */ + return; + } + + gic_drop_prio(s, cpu, 0); + + if (!gic_eoi_split(s, cpu, attrs)) { + bool valid =3D gic_virq_is_valid(s, irq, cpu); + if (prio_drop && !valid) { + /* We are in a situation where: + * - V_CTRL.EOIMode is false (no EOI split), + * - The call to gic_drop_prio() cleared a bit in GICH_A= PR, + * - This vIRQ does not have an LR entry which is either + * active or pending and active. + * In that case, we must increment EOICount. + */ + int rcpu =3D gic_get_vcpu_real_id(cpu); + s->h_hcr[rcpu] +=3D 1 << R_GICH_HCR_EOICount_SHIFT; + } else if (valid) { + gic_clear_active(s, irq, cpu); + } + } + + return; + } + if (irq >=3D s->num_irq) { /* This handles two cases: * 1. If software writes the ID of a spurious interrupt [ie 1023] * to the GICC_EOIR, the GIC ignores that write. * 2. If software writes the number of a non-existent interrupt --=20 2.18.0