From nobody Wed Feb 11 03:25:54 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 153268598170751.07193315996847; Fri, 27 Jul 2018 03:06:21 -0700 (PDT) Received: from localhost ([::1]:40105 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fizdc-0004v7-Kr for importer@patchew.org; Fri, 27 Jul 2018 06:06:20 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58395) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fizSm-0003vX-AI for qemu-devel@nongnu.org; Fri, 27 Jul 2018 05:55:11 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fizSi-0006Md-0M for qemu-devel@nongnu.org; Fri, 27 Jul 2018 05:55:08 -0400 Received: from greensocs.com ([193.104.36.180]:47522) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fizSY-00068w-Tj; Fri, 27 Jul 2018 05:54:55 -0400 Received: from localhost (localhost [127.0.0.1]) by greensocs.com (Postfix) with ESMTP id A7ABA44A0ED; Fri, 27 Jul 2018 11:54:49 +0200 (CEST) Received: from greensocs.com ([127.0.0.1]) by localhost (gs-01.greensocs.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id x9UaHX8zwHrr; Fri, 27 Jul 2018 11:54:48 +0200 (CEST) Received: by greensocs.com (Postfix, from userid 998) id 5CCE7443555; Fri, 27 Jul 2018 11:54:47 +0200 (CEST) Received: from michell-laptop.bar.greensocs.com (antfield.tima.u-ga.fr [147.171.129.253]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: luc.michel@greensocs.com) by greensocs.com (Postfix) with ESMTPSA id EA333400DC8; Fri, 27 Jul 2018 11:54:46 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1532685289; bh=xAHr68KhTy99xqhWJCA5rOyjUrOn4IWYSYzyr9p/TEY=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=weUOvuL5BHOLE6pGyYGoLGiuc5KbN8aFDGSUYufU0cMtMLNA/84fl/+haE1xHSVFR 78u0p00g91DzYrrZ3Y0SO/kL/OnffhEHKaJGZ7zYQ0cyj3qLMDwJ9y0S1zVvAY+Cm9 LsLq8DevVuRV1gOZ7sF9fq84ORCy2/WypbGy9CM8= X-Virus-Scanned: amavisd-new at greensocs.com Authentication-Results: gs-01.greensocs.com (amavisd-new); dkim=pass (1024-bit key) header.d=greensocs.com header.b=wSat81Rr; dkim=pass (1024-bit key) header.d=greensocs.com header.b=wSat81Rr DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1532685287; bh=xAHr68KhTy99xqhWJCA5rOyjUrOn4IWYSYzyr9p/TEY=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=wSat81RrlO42dGXoRSqss54l1nHdkobMs8qcVIvCJugyw9s61ywCZZxJ+1aVMLAbM Z+bYxT6St/Bth0BZ/CY4W6xyQ5v1F3upeOFRN9BASTg6x3l4PHtMvUGeMhRLuwy+Ev PcXXCCNO++lobZ9X5T6dqwP6MSXQRr06x9cG+JJA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1532685287; bh=xAHr68KhTy99xqhWJCA5rOyjUrOn4IWYSYzyr9p/TEY=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=wSat81RrlO42dGXoRSqss54l1nHdkobMs8qcVIvCJugyw9s61ywCZZxJ+1aVMLAbM Z+bYxT6St/Bth0BZ/CY4W6xyQ5v1F3upeOFRN9BASTg6x3l4PHtMvUGeMhRLuwy+Ev PcXXCCNO++lobZ9X5T6dqwP6MSXQRr06x9cG+JJA= From: Luc Michel To: qemu-devel@nongnu.org Date: Fri, 27 Jul 2018 11:54:12 +0200 Message-Id: <20180727095421.386-12-luc.michel@greensocs.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180727095421.386-1-luc.michel@greensocs.com> References: <20180727095421.386-1-luc.michel@greensocs.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 193.104.36.180 Subject: [Qemu-devel] [PATCH v5 11/20] intc/arm_gic: Implement virtualization extensions in gic_acknowledge_irq X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , mark.burton@greensocs.com, saipava@xilinx.com, edgari@xilinx.com, qemu-arm@nongnu.org, Jan Kiszka , Luc Michel Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (found 2 invalid signatures) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Implement virtualization extensions in the gic_acknowledge_irq() function. This function changes the state of the highest priority IRQ from pending to active. When the current CPU is a vCPU, modifying the state of an IRQ modifies the corresponding LR entry. However if we clear the pending flag before setting the active one, we lose track of the LR entry as it becomes invalid. The next call to gic_get_lr_entry() will fail. To overcome this issue, we call gic_activate_irq() before gic_clear_pending(). This does not change the general behaviour of gic_acknowledge_irq. We also move the SGI case in gic_clear_pending_sgi() to enhance code readability as the virtualization extensions support adds a if-else level. Signed-off-by: Luc Michel Reviewed-by: Peter Maydell --- hw/intc/arm_gic.c | 52 ++++++++++++++++++++++++++++++----------------- 1 file changed, 33 insertions(+), 19 deletions(-) diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index de73dc9f54..d80acde989 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -363,21 +363,48 @@ static void gic_drop_prio(GICState *s, int cpu, int g= roup) } =20 s->running_priority[cpu] =3D gic_get_prio_from_apr_bits(s, cpu); } =20 +static inline uint32_t gic_clear_pending_sgi(GICState *s, int irq, int cpu) +{ + int src; + uint32_t ret; + + if (!gic_is_vcpu(cpu)) { + /* Lookup the source CPU for the SGI and clear this in the + * sgi_pending map. Return the src and clear the overall pending + * state on this CPU if the SGI is not pending from any CPUs. + */ + assert(s->sgi_pending[irq][cpu] !=3D 0); + src =3D ctz32(s->sgi_pending[irq][cpu]); + s->sgi_pending[irq][cpu] &=3D ~(1 << src); + if (s->sgi_pending[irq][cpu] =3D=3D 0) { + gic_clear_pending(s, irq, cpu); + } + ret =3D irq | ((src & 0x7) << 10); + } else { + uint32_t *lr_entry =3D gic_get_lr_entry(s, irq, cpu); + src =3D GICH_LR_CPUID(*lr_entry); + + gic_clear_pending(s, irq, cpu); + ret =3D irq | (src << 10); + } + + return ret; +} + uint32_t gic_acknowledge_irq(GICState *s, int cpu, MemTxAttrs attrs) { - int ret, irq, src; - int cm =3D 1 << cpu; + int ret, irq; =20 /* gic_get_current_pending_irq() will return 1022 or 1023 appropriately * for the case where this GIC supports grouping and the pending inter= rupt * is in the wrong group. */ irq =3D gic_get_current_pending_irq(s, cpu, attrs); - trace_gic_acknowledge_irq(cpu, irq); + trace_gic_acknowledge_irq(gic_get_vcpu_real_id(cpu), irq); =20 if (irq >=3D GIC_MAXIRQ) { DPRINTF("ACK, no pending interrupt or it is hidden: %d\n", irq); return irq; } @@ -385,40 +412,27 @@ uint32_t gic_acknowledge_irq(GICState *s, int cpu, Me= mTxAttrs attrs) if (gic_get_priority(s, irq, cpu) >=3D s->running_priority[cpu]) { DPRINTF("ACK, pending interrupt (%d) has insufficient priority\n",= irq); return 1023; } =20 + gic_activate_irq(s, cpu, irq); + if (s->revision =3D=3D REV_11MPCORE) { /* Clear pending flags for both level and edge triggered interrupt= s. * Level triggered IRQs will be reasserted once they become inacti= ve. */ gic_clear_pending(s, irq, cpu); ret =3D irq; } else { if (irq < GIC_NR_SGIS) { - /* Lookup the source CPU for the SGI and clear this in the - * sgi_pending map. Return the src and clear the overall pend= ing - * state on this CPU if the SGI is not pending from any CPUs. - */ - assert(s->sgi_pending[irq][cpu] !=3D 0); - src =3D ctz32(s->sgi_pending[irq][cpu]); - s->sgi_pending[irq][cpu] &=3D ~(1 << src); - if (s->sgi_pending[irq][cpu] =3D=3D 0) { - gic_clear_pending(s, irq, cpu); - } - ret =3D irq | ((src & 0x7) << 10); + ret =3D gic_clear_pending_sgi(s, irq, cpu); } else { - /* Clear pending state for both level and edge triggered - * interrupts. (level triggered interrupts with an active line - * remain pending, see gic_test_pending) - */ gic_clear_pending(s, irq, cpu); ret =3D irq; } } =20 - gic_activate_irq(s, cpu, irq); gic_update(s); DPRINTF("ACK %d\n", irq); return ret; } =20 --=20 2.18.0