From nobody Sun May 5 14:45:21 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 15325727303571014.2020990216945; Wed, 25 Jul 2018 19:38:50 -0700 (PDT) Received: from localhost ([::1]:57704 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fiWAx-0006kR-Et for importer@patchew.org; Wed, 25 Jul 2018 22:38:47 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53351) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fiW9T-0005dP-K3 for qemu-devel@nongnu.org; Wed, 25 Jul 2018 22:37:18 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fiW9Q-00035v-LI for qemu-devel@nongnu.org; Wed, 25 Jul 2018 22:37:15 -0400 Received: from mail-pl0-x22c.google.com ([2607:f8b0:400e:c01::22c]:46341) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fiW9Q-00034n-Ef; Wed, 25 Jul 2018 22:37:12 -0400 Received: by mail-pl0-x22c.google.com with SMTP id t17-v6so99584ply.13; Wed, 25 Jul 2018 19:37:12 -0700 (PDT) Received: from aurora.jms.id.au ([45.124.203.18]) by smtp.gmail.com with ESMTPSA id u69-v6sm97273pgd.43.2018.07.25.19.37.06 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 25 Jul 2018 19:37:10 -0700 (PDT) Received: by aurora.jms.id.au (sSMTP sendmail emulation); Thu, 26 Jul 2018 12:07:03 +0930 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=KwnVk0FZbRL5sACB19TJDzQlDaPoBQkUgoOUVam8cLY=; b=Mub7niAUSvR0k4nmQtWOkJUjf21QcLdwdguPVMKki8HlBi/mIznNil/i6LdVsAnQBh kMLYbvDKEbAbFfUYd2y6OYDE+WYbO1MzeSRSrBURSpMkyfz0f/46feGlPMu7o856/mPi /BIU4hqZDq4R9DRxa8JCtgyjwt2PyGMydGHV70KPTuTL3Ah0dWJtfPyQIUxq7EBZnCZ8 QhPLHiPvxMYPnVjR0U87rvzmIWoUguGEOgrOwZbyMOZ3h+EXrti4IZqLS/qdNkvjpnOM A1QarnVXDQNXIgO+VJGMnxJ7mzl/cXrZsW1ei/S8+UW0mi5lWsyHQQGRCC7IRvCy+H/e MqOg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=KwnVk0FZbRL5sACB19TJDzQlDaPoBQkUgoOUVam8cLY=; b=Sdsk1kH5GUHAcX+571/hpsWXeHZkbnSCY/WIXtVPuKCY6YUjgLsNFBIje3SoziEZ15 7ngsjo75Hqtlpo6SkNo7Iz6ndSby39+mVXOifsHJ6giL8qVzWdLEZrBAaYDeTtKmFLQl y3bHhq7/GFzvyFQQSYpP8FmUZ6//UQzL3PXdYnEw4bBSw8g0ulhHzJ2y3gOA+ogvHLs0 7QzDO8D4UBv4Nz1GkiLap68FiOxszGAdtJpgnfrP67aUO2piYY+M9IppydDGUdlA21tx 7QdwPwDBTGwLhACt42JM9a2AtJ2TTGFWZOOqKD02z5tIYiWLHxWix1ZE5XlHYZQpzuga 3Yiw== X-Gm-Message-State: AOUpUlETuG94nbF2FCmP8TOCoCYRmhQ4LpZHSu2RH6WrKz44RfeZyGk4 NqOhrv+jyCxnCczCc4OBVj4= X-Google-Smtp-Source: AAOMgpflb/6YOBMNq9Hf/KYL4CFDL6MgFnJJBj0p9g0eR2lNGQJ9IP7fRlQjVzT8THpQg3CMXB9qZQ== X-Received: by 2002:a17:902:8a4:: with SMTP id 33-v6mr77755pll.343.1532572631388; Wed, 25 Jul 2018 19:37:11 -0700 (PDT) From: Joel Stanley To: Peter Maydell Date: Thu, 26 Jul 2018 12:06:43 +0930 Message-Id: <20180726023645.13927-2-joel@jms.id.au> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180726023645.13927-1-joel@jms.id.au> References: <20180726023645.13927-1-joel@jms.id.au> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c01::22c Subject: [Qemu-devel] [PATCH v3 1/3] MAINTAINERS: Add NRF51 entry X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stefan Hajnoczi , =?UTF-8?q?Steffen=20G=C3=B6rtz?= , qemu-devel@nongnu.org, qemu-arm@nongnu.org, Jim Mussared , Julia Suvorova Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This contains the NRF51, and the machine that uses it, the BBC micro:bit. Reviewed-by: Stefan Hajnoczi Signed-off-by: Joel Stanley --- v3: fix spelling of mailing list add stefan's reviewed-by --- MAINTAINERS | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index c48d9271cf15..5a0d2e327d4a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -656,6 +656,14 @@ F: include/hw/*/*aspeed* F: hw/net/ftgmac100.c F: include/hw/net/ftgmac100.h =20 +NRF51 +M: Joel Stanley +L: qemu-arm@nongnu.org +S: Maintained +F: hw/arm/nrf51_soc.c +F: hw/arm/microbit.c +F: include/hw/arm/nrf51_soc.h + CRIS Machines ------------- Axis Dev88 --=20 2.17.1 From nobody Sun May 5 14:45:21 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1532572866348198.42557315496003; Wed, 25 Jul 2018 19:41:06 -0700 (PDT) Received: from localhost ([::1]:57721 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fiWDA-0000Dh-UD for importer@patchew.org; Wed, 25 Jul 2018 22:41:04 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53374) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fiW9d-0005jS-Gn for qemu-devel@nongnu.org; Wed, 25 Jul 2018 22:37:28 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fiW9a-0003Ap-HW for qemu-devel@nongnu.org; Wed, 25 Jul 2018 22:37:25 -0400 Received: from mail-pg1-x543.google.com ([2607:f8b0:4864:20::543]:41157) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fiW9a-0003AF-8j; Wed, 25 Jul 2018 22:37:22 -0400 Received: by mail-pg1-x543.google.com with SMTP id z8-v6so147372pgu.8; Wed, 25 Jul 2018 19:37:21 -0700 (PDT) Received: from aurora.jms.id.au ([45.124.203.18]) by smtp.gmail.com with ESMTPSA id v3-v6sm97677pgb.54.2018.07.25.19.37.15 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 25 Jul 2018 19:37:19 -0700 (PDT) Received: by aurora.jms.id.au (sSMTP sendmail emulation); Thu, 26 Jul 2018 12:07:11 +0930 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=2i1+Cu/59CCCTmqjBSM6Ly+EMPHBZRYPxijqsvtLTrc=; b=LtuiPLSwtB9SN2K6Vb7mBK+JuAcf5VNFsCozyz8gBLuSL8z/91/iQ8NN1RpInsf55p y6GitdrmUyKfW2J6kbE8Y9ac6aVPYDuNno6da73YMaAHgA2P9kki4SLIhXuR5iI2jlm2 TgoZ0V8b05EQ+Szow6Vw1WhSypQJYogYbmpxir3gUMqxqewWAUvtJqqYudSJ1X5AmFku smBzTPKNjN8i1sAAJDKnRSeZGQrrB+wnvJvAkLOGBhsvfmk0fk5FxXfv9tfoBCvyqdlw Bsiw26fA0WxaxF6sNxy1V2fcLYneD//shcfId44ql6sN0IacQQXhlC65ebQodYvkzbMO wXGA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=2i1+Cu/59CCCTmqjBSM6Ly+EMPHBZRYPxijqsvtLTrc=; b=U7Y0PigEG+axhPyGyDDaDZAXb4fJWtpQnVqHEgishluMFar13PPopbTy+snmb4g2gS PIbUTe0mA5EN7jQtWu5IhCJTquhoKrwgD3osXiMEj3faCovJjFQpZc25hi2w7bI2ywZw 3aEDm7FvL0IKcraMciKBUTFUFF0L4FKniDQhNFwygZ0aSdncDZu9aef9pYAs3hiaFmC8 gCmX40KoMVYpjCmJuh8j3vFuinIfgq7nQd7QLfe46RMYxrPYCpwJTy8x5L6QRp8DeDZK esNTxdHCazsE0Ml/jg709VxODAQkgS3HLFQsu0h0qxir2PtGYAhSwaRB5rbEIfyZxDdw fStQ== X-Gm-Message-State: AOUpUlEp3BZy+5yMwEDqOJkMHRoex5w2dbuopD9IRN9obkN/iahwNcZy /6VjjYcAVD2O2pk1Pd5JcUc= X-Google-Smtp-Source: AAOMgpfrWzHIkZNcmtle/ttyjbgKzqxGjdvAHCMq1q754ix80GFb8nx4jlx8xOJzbmi6AR97pLfcYQ== X-Received: by 2002:a62:990f:: with SMTP id d15-v6mr138055pfe.162.1532572640973; Wed, 25 Jul 2018 19:37:20 -0700 (PDT) From: Joel Stanley To: Peter Maydell Date: Thu, 26 Jul 2018 12:06:44 +0930 Message-Id: <20180726023645.13927-3-joel@jms.id.au> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180726023645.13927-1-joel@jms.id.au> References: <20180726023645.13927-1-joel@jms.id.au> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 Subject: [Qemu-devel] [PATCH v3 2/3] arm: Add Nordic Semiconductor nRF51 SoC X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stefan Hajnoczi , =?UTF-8?q?Steffen=20G=C3=B6rtz?= , qemu-devel@nongnu.org, qemu-arm@nongnu.org, Jim Mussared , Julia Suvorova Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The nRF51 is a Cortex-M0 microcontroller with an on-board radio module, plus other common ARM SoC peripherals. http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.pdf This defines a basic model of the CPU and memory, with no peripherals implemented at this stage. Signed-off-by: Joel Stanley --- v2: put memory as struct fileds in state structure pass OBJECT(s) as owner, not NULL Add missing addresses for ficr Fix flash and sram sizes for microbit Embed cpu object in state object an initalise it without use of armv7m_in= it Link to datasheet v3: rebase nrf51 on m0 changes remove unused kernel_filename clarify flash and sram size make flash and sram size properties of the soc state --- default-configs/arm-softmmu.mak | 1 + hw/arm/Makefile.objs | 1 + hw/arm/nrf51_soc.c | 119 ++++++++++++++++++++++++++++++++ include/hw/arm/nrf51_soc.h | 42 +++++++++++ 4 files changed, 163 insertions(+) create mode 100644 hw/arm/nrf51_soc.c create mode 100644 include/hw/arm/nrf51_soc.h diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.= mak index e704cb6e34d7..3432721d7d08 100644 --- a/default-configs/arm-softmmu.mak +++ b/default-configs/arm-softmmu.mak @@ -102,6 +102,7 @@ CONFIG_STM32F2XX_SYSCFG=3Dy CONFIG_STM32F2XX_ADC=3Dy CONFIG_STM32F2XX_SPI=3Dy CONFIG_STM32F205_SOC=3Dy +CONFIG_NRF51_SOC=3Dy =20 CONFIG_CMSDK_APB_TIMER=3Dy CONFIG_CMSDK_APB_UART=3Dy diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs index b1e4f8f006aa..e31875ec69bc 100644 --- a/hw/arm/Makefile.objs +++ b/hw/arm/Makefile.objs @@ -36,3 +36,4 @@ obj-$(CONFIG_MSF2) +=3D msf2-soc.o msf2-som.o obj-$(CONFIG_IOTKIT) +=3D iotkit.o obj-$(CONFIG_FSL_IMX7) +=3D fsl-imx7.o mcimx7d-sabre.o obj-$(CONFIG_ARM_SMMUV3) +=3D smmu-common.o smmuv3.o +obj-$(CONFIG_NRF51_SOC) +=3D nrf51_soc.o diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c new file mode 100644 index 000000000000..03fa1dfc7456 --- /dev/null +++ b/hw/arm/nrf51_soc.c @@ -0,0 +1,119 @@ +/* + * Nordic Semiconductor nRF51 SoC + * http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.1.pdf + * + * Copyright 2018 Joel Stanley + * + * This code is licensed under the GPL version 2 or later. See + * the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "qemu-common.h" +#include "hw/arm/arm.h" +#include "hw/sysbus.h" +#include "hw/boards.h" +#include "hw/devices.h" +#include "hw/misc/unimp.h" +#include "exec/address-spaces.h" +#include "sysemu/sysemu.h" +#include "qemu/log.h" +#include "cpu.h" + +#include "hw/arm/nrf51_soc.h" + +#define IOMEM_BASE 0x40000000 +#define IOMEM_SIZE 0x20000000 + +#define FICR_BASE 0x10000000 +#define FICR_SIZE 0x000000fc + +#define FLASH_BASE 0x00000000 +#define SRAM_BASE 0x20000000 + +/* The size and base is for the NRF51822 part. If other parts + * are supported in the future, add a sub-class of NRF51SoC for + * the specific variants */ +#define NRF51822_FLASH_SIZE (256 * 1024) +#define NRF51822_SRAM_SIZE (16 * 1024) + +static void nrf51_soc_realize(DeviceState *dev_soc, Error **errp) +{ + NRF51State *s =3D NRF51_SOC(dev_soc); + Error *err =3D NULL; + + if (!s->board_memory) { + error_setg(errp, "memory property was not set"); + return; + } + + object_property_set_link(OBJECT(&s->cpu), OBJECT(&s->container), "memo= ry", + &err); + object_property_set_bool(OBJECT(&s->cpu), true, "realized", &err); + + memory_region_add_subregion_overlap(&s->container, 0, s->board_memory,= -1); + + memory_region_init_ram(&s->flash, OBJECT(s), "nrf51.flash", s->flash_s= ize, + &err); + if (err) { + error_propagate(errp, err); + return; + } + memory_region_set_readonly(&s->flash, true); + memory_region_add_subregion(&s->container, FLASH_BASE, &s->flash); + + memory_region_init_ram(&s->sram, NULL, "nrf51.sram", s->sram_size, &er= r); + if (err) { + error_propagate(errp, err); + return; + } + memory_region_add_subregion(&s->container, SRAM_BASE, &s->sram); + + create_unimplemented_device("nrf51_soc.io", IOMEM_BASE, IOMEM_SIZE); + create_unimplemented_device("nrf51_soc.ficr", FICR_BASE, FICR_SIZE); + create_unimplemented_device("nrf51_soc.private", 0xF0000000, 0x1000000= 0); +} + +static void nrf51_soc_init(Object *obj) +{ + NRF51State *s =3D NRF51_SOC(obj); + + memory_region_init(&s->container, obj, "nrf51-container", UINT64_MAX); + + object_initialize(&s->cpu, sizeof(s->cpu), TYPE_ARM_M_PROFILE); + object_property_add_child(OBJECT(s), "armv6m", OBJECT(&s->cpu), &error= _abort); + qdev_set_parent_bus(DEVICE(&s->cpu), sysbus_get_default()); + qdev_prop_set_string(DEVICE(&s->cpu), "cpu-type", ARM_CPU_TYPE_NAME("c= ortex-m0")); + qdev_prop_set_uint32(DEVICE(&s->cpu), "num-irq", 96); +} + +static Property nrf51_soc_properties[] =3D { + DEFINE_PROP_LINK("memory", NRF51State, board_memory, TYPE_MEMORY_REGIO= N, + MemoryRegion *), + DEFINE_PROP_UINT32("sram-size", NRF51State, sram_size, NRF51822_SRAM_S= IZE), + DEFINE_PROP_UINT32("flash-size", NRF51State, flash_size, NRF51822_FLAS= H_SIZE), + DEFINE_PROP_END_OF_LIST(), +}; + +static void nrf51_soc_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->realize =3D nrf51_soc_realize; + dc->props =3D nrf51_soc_properties; +} + +static const TypeInfo nrf51_soc_info =3D { + .name =3D TYPE_NRF51_SOC, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(NRF51State), + .instance_init =3D nrf51_soc_init, + .class_init =3D nrf51_soc_class_init, +}; + +static void nrf51_soc_types(void) +{ + type_register_static(&nrf51_soc_info); +} +type_init(nrf51_soc_types) diff --git a/include/hw/arm/nrf51_soc.h b/include/hw/arm/nrf51_soc.h new file mode 100644 index 000000000000..838bccd815df --- /dev/null +++ b/include/hw/arm/nrf51_soc.h @@ -0,0 +1,42 @@ +/* + * Nordic Semiconductor nRF51 SoC + * + * Copyright 2018 Joel Stanley + * + * This code is licensed under the GPL version 2 or later. See + * the COPYING file in the top-level directory. + */ + +#ifndef NRF51_SOC_H +#define NRF51_SOC_H + +#include "qemu/osdep.h" +#include "hw/sysbus.h" +#include "hw/arm/arm-m-profile.h" + +#define TYPE_NRF51_SOC "nrf51-soc" +#define NRF51_SOC(obj) \ + OBJECT_CHECK(NRF51State, (obj), TYPE_NRF51_SOC) + +typedef struct NRF51State { + /*< private >*/ + SysBusDevice parent_obj; + + /*< public >*/ + ARMMProfileState cpu; + + MemoryRegion iomem; + MemoryRegion sram; + MemoryRegion flash; + + uint32_t sram_size; + uint32_t flash_size; + + MemoryRegion *board_memory; + + MemoryRegion container; + +} NRF51State; + +#endif + --=20 2.17.1 From nobody Sun May 5 14:45:21 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1532572861603149.24100027459576; Wed, 25 Jul 2018 19:41:01 -0700 (PDT) Received: from localhost ([::1]:57720 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fiWD2-00005G-Ce for importer@patchew.org; Wed, 25 Jul 2018 22:40:56 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53399) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fiW9l-0005oi-Bn for qemu-devel@nongnu.org; Wed, 25 Jul 2018 22:37:36 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fiW9i-0003LY-Ci for qemu-devel@nongnu.org; Wed, 25 Jul 2018 22:37:33 -0400 Received: from mail-pf1-x444.google.com ([2607:f8b0:4864:20::444]:35583) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1fiW9i-0003LO-6X; Wed, 25 Jul 2018 22:37:30 -0400 Received: by mail-pf1-x444.google.com with SMTP id q7-v6so74013pff.2; Wed, 25 Jul 2018 19:37:30 -0700 (PDT) Received: from aurora.jms.id.au ([45.124.203.18]) by smtp.gmail.com with ESMTPSA id x87-v6sm106681pfa.143.2018.07.25.19.37.24 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 25 Jul 2018 19:37:28 -0700 (PDT) Received: by aurora.jms.id.au (sSMTP sendmail emulation); Thu, 26 Jul 2018 12:07:21 +0930 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=uVpIy0tbum8TS+4LeuR9ToTnLJtiAlEi8k9IZIn1ZjE=; b=e+rSrOSoOddjat6fksfoZiVEkrkWwBPaaUree7BLNDWo8/KygHjyAm6VOLcP9xIJdz xlMjhWArb5TyFaxqLc0iY1FWHAy2H9x6IZKiS13rTE2cyyi938PsCp1pJ72MZJ9DAfR3 udB8IM3fLB/F58lCtZsLH4PfiG4Mle89x0JKtIk6qqMVaFgZyiRX/3BHLI1Ee3QFNdDk yE3C/0SpvEKNfhVDLnjh5Jy4zQn13XoGHrQ9cCrW4R7N0vWH6Pig7zmvKYAj8ePhXS+G vqbYu/jjs/fDHJnQefAPGhfI2JPDQZ8N5ilOiftBslt+WHJ8U/Uo+OEkTNxGMZsjXGf8 FkIQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=uVpIy0tbum8TS+4LeuR9ToTnLJtiAlEi8k9IZIn1ZjE=; b=qiLsmNfYyKpGRVHOjKzx7lNmPcueMDR1flP+4PsJpOsPKz1M5BuF5E0oENwivyJLWV j6v86v5CzUjKhrwjdDRRevmkukFcViNQvw4mtOEkiKTLpIzyy0Cf8ZUWydoFpWnu2Wl3 oGXVHtcGbnm5PwPGC+3I9PPywCfS2XAYYEcxGqVFTZUQi0RBD2b8YT4J0YnKHxmvTRE3 Z94C9n/D4dj/LFGmNSqXZ6tj+PKwZZSoBSDrOoPa4i1COFhRajXlGKFjwji1qiYWDMoP OnIs+0IY+lBQDtwuO80kY04QufzfMQCK2VSI1XqlG3OZ+zkXqTkIALWBzZGQp9Bmgmxo w6Ew== X-Gm-Message-State: AOUpUlHRSAjLi2udZs8VvsFFgKtBP9tnbLEEmTQ7d74hDG/EQnquNc+p /pjDe8kmdXeIN30p+R1BCn4= X-Google-Smtp-Source: AAOMgpfh1jRiyUNyGzC9wYc5spp5iLnH9lYhj7ijBO/4YyBiexhRuz3E29H+heGEhE2Rxi+9hbxVXg== X-Received: by 2002:a62:6eca:: with SMTP id j193-v6mr127694pfc.256.1532572649147; Wed, 25 Jul 2018 19:37:29 -0700 (PDT) From: Joel Stanley To: Peter Maydell Date: Thu, 26 Jul 2018 12:06:45 +0930 Message-Id: <20180726023645.13927-4-joel@jms.id.au> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180726023645.13927-1-joel@jms.id.au> References: <20180726023645.13927-1-joel@jms.id.au> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::444 Subject: [Qemu-devel] [PATCH v3 3/3] arm: Add BBC micro:bit machine X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stefan Hajnoczi , =?UTF-8?q?Steffen=20G=C3=B6rtz?= , qemu-devel@nongnu.org, qemu-arm@nongnu.org, Jim Mussared , Julia Suvorova Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This adds the base for a machine model of the BBC micro:bit: https://en.wikipedia.org/wiki/Micro_Bit This is a system with a nRF51 SoC containing the main processor, with various peripherals on board. Reviewed-by: Stefan Hajnoczi Signed-off-by: Joel Stanley --- v2: - Instead of setting kernel filename property, load the image directly - Add link to hardware overview website v3: - Rebase microbit on m0 changes - Remove hard-coded flash size and retrieve from the soc - Add Stefan's reviewed-by --- hw/arm/Makefile.objs | 2 +- hw/arm/microbit.c | 54 ++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 55 insertions(+), 1 deletion(-) create mode 100644 hw/arm/microbit.c diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs index e31875ec69bc..2798a257921d 100644 --- a/hw/arm/Makefile.objs +++ b/hw/arm/Makefile.objs @@ -36,4 +36,4 @@ obj-$(CONFIG_MSF2) +=3D msf2-soc.o msf2-som.o obj-$(CONFIG_IOTKIT) +=3D iotkit.o obj-$(CONFIG_FSL_IMX7) +=3D fsl-imx7.o mcimx7d-sabre.o obj-$(CONFIG_ARM_SMMUV3) +=3D smmu-common.o smmuv3.o -obj-$(CONFIG_NRF51_SOC) +=3D nrf51_soc.o +obj-$(CONFIG_NRF51_SOC) +=3D nrf51_soc.o microbit.o diff --git a/hw/arm/microbit.c b/hw/arm/microbit.c new file mode 100644 index 000000000000..ecf64e883f4f --- /dev/null +++ b/hw/arm/microbit.c @@ -0,0 +1,54 @@ +/* + * BBC micro:bit machine + * http://tech.microbit.org/hardware/ + * + * Copyright 2018 Joel Stanley + * + * This code is licensed under the GPL version 2 or later. See + * the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "hw/boards.h" +#include "hw/arm/arm.h" +#include "exec/address-spaces.h" + +#include "hw/arm/nrf51_soc.h" + +typedef struct { + MachineState parent; + + NRF51State nrf51; +} MICROBITMachineState; + +#define TYPE_MICROBIT_MACHINE "microbit" + +#define MICROBIT_MACHINE(obj) \ + OBJECT_CHECK(MICROBITMachineState, obj, TYPE_MICROBIT_MACHINE) + +static void microbit_init(MachineState *machine) +{ + MICROBITMachineState *s =3D g_new(MICROBITMachineState, 1); + MemoryRegion *system_memory =3D get_system_memory(); + Object *soc; + + object_initialize(&s->nrf51, sizeof(s->nrf51), TYPE_NRF51_SOC); + soc =3D OBJECT(&s->nrf51); + object_property_add_child(OBJECT(machine), "nrf51", soc, &error_fatal); + object_property_set_link(soc, OBJECT(system_memory), + "memory", &error_abort); + + object_property_set_bool(soc, true, "realized", &error_abort); + + arm_m_profile_load_kernel(ARM_CPU(first_cpu), machine->kernel_filename, + NRF51_SOC(soc)->flash_size); +} + +static void microbit_machine_init(MachineClass *mc) +{ + mc->desc =3D "BBC micro:bit"; + mc->init =3D microbit_init; + mc->max_cpus =3D 1; +} +DEFINE_MACHINE("microbit", microbit_machine_init); --=20 2.17.1