From nobody Wed Nov 5 05:22:26 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1532433993077225.39157383951317; Tue, 24 Jul 2018 05:06:33 -0700 (PDT) Received: from localhost ([::1]:39782 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fhw4j-0004XL-Nk for importer@patchew.org; Tue, 24 Jul 2018 08:05:57 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52174) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fhvyx-0008Di-V0 for qemu-devel@nongnu.org; Tue, 24 Jul 2018 08:00:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fhvyx-0003A5-7r for qemu-devel@nongnu.org; Tue, 24 Jul 2018 08:00:00 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:43714) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fhvyv-00034o-4u; Tue, 24 Jul 2018 07:59:57 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fhvyq-0008Ow-Gi; Tue, 24 Jul 2018 12:59:52 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 24 Jul 2018 12:59:46 +0100 Message-Id: <20180724115950.17316-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180724115950.17316-1-peter.maydell@linaro.org> References: <20180724115950.17316-1-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH 1/5] target/arm: Mask virtual interrupts if HCR_EL2.TGE is set X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" If the "trap general exceptions" bit HCR_EL2.TGE is set, we must mask all virtual interrupts (as per DDI0487C.a D1.14.3). Implement this in arm_excp_unmasked(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu.h | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index e310ffc29d2..efb2a8d3f3d 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2261,13 +2261,15 @@ static inline bool arm_excp_unmasked(CPUState *cs, = unsigned int excp_idx, break; =20 case EXCP_VFIQ: - if (secure || !(env->cp15.hcr_el2 & HCR_FMO)) { + if (secure || !(env->cp15.hcr_el2 & HCR_FMO) + || (env->cp15.hcr_el2 & HCR_TGE)) { /* VFIQs are only taken when hypervized and non-secure. */ return false; } return !(env->daif & PSTATE_F); case EXCP_VIRQ: - if (secure || !(env->cp15.hcr_el2 & HCR_IMO)) { + if (secure || !(env->cp15.hcr_el2 & HCR_IMO) + || (env->cp15.hcr_el2 & HCR_TGE)) { /* VIRQs are only taken when hypervized and non-secure. */ return false; } --=20 2.17.1