From nobody Wed Nov 5 02:34:55 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1532433993077225.39157383951317; Tue, 24 Jul 2018 05:06:33 -0700 (PDT) Received: from localhost ([::1]:39782 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fhw4j-0004XL-Nk for importer@patchew.org; Tue, 24 Jul 2018 08:05:57 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52174) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fhvyx-0008Di-V0 for qemu-devel@nongnu.org; Tue, 24 Jul 2018 08:00:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fhvyx-0003A5-7r for qemu-devel@nongnu.org; Tue, 24 Jul 2018 08:00:00 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:43714) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fhvyv-00034o-4u; Tue, 24 Jul 2018 07:59:57 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fhvyq-0008Ow-Gi; Tue, 24 Jul 2018 12:59:52 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 24 Jul 2018 12:59:46 +0100 Message-Id: <20180724115950.17316-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180724115950.17316-1-peter.maydell@linaro.org> References: <20180724115950.17316-1-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH 1/5] target/arm: Mask virtual interrupts if HCR_EL2.TGE is set X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" If the "trap general exceptions" bit HCR_EL2.TGE is set, we must mask all virtual interrupts (as per DDI0487C.a D1.14.3). Implement this in arm_excp_unmasked(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu.h | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index e310ffc29d2..efb2a8d3f3d 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2261,13 +2261,15 @@ static inline bool arm_excp_unmasked(CPUState *cs, = unsigned int excp_idx, break; =20 case EXCP_VFIQ: - if (secure || !(env->cp15.hcr_el2 & HCR_FMO)) { + if (secure || !(env->cp15.hcr_el2 & HCR_FMO) + || (env->cp15.hcr_el2 & HCR_TGE)) { /* VFIQs are only taken when hypervized and non-secure. */ return false; } return !(env->daif & PSTATE_F); case EXCP_VIRQ: - if (secure || !(env->cp15.hcr_el2 & HCR_IMO)) { + if (secure || !(env->cp15.hcr_el2 & HCR_IMO) + || (env->cp15.hcr_el2 & HCR_TGE)) { /* VIRQs are only taken when hypervized and non-secure. */ return false; } --=20 2.17.1 From nobody Wed Nov 5 02:34:55 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 153243375165886.30802012474624; Tue, 24 Jul 2018 05:02:31 -0700 (PDT) Received: from localhost ([::1]:39756 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fhw1O-0001gR-GT for importer@patchew.org; Tue, 24 Jul 2018 08:02:30 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52167) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fhvyx-0008CF-G4 for qemu-devel@nongnu.org; Tue, 24 Jul 2018 08:00:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fhvyw-000394-PZ for qemu-devel@nongnu.org; Tue, 24 Jul 2018 07:59:59 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:43714) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fhvyu-00034o-7G; Tue, 24 Jul 2018 07:59:56 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fhvyr-0008PD-5Z; Tue, 24 Jul 2018 12:59:53 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 24 Jul 2018 12:59:47 +0100 Message-Id: <20180724115950.17316-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180724115950.17316-1-peter.maydell@linaro.org> References: <20180724115950.17316-1-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH 2/5] target/arm: Honour HCR_EL2.TGE and MDCR_EL2.TDE in debug register access checks X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Some debug registers can be trapped via MDCR_EL2 bits TDRA, TDOSA, and TDA, which we implement in the functions access_tdra(), access_tdosa() and access_tda(). If MDCR_EL2.TDE or HCR_EL2.TGE are 1, the TDRA, TDOSA and TDA bits should behave as if they were 1. Implement this by having the access functions check MDCR_EL2.TDE and HCR_EL2.TGE. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper.c | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 22d812240af..e2930e99388 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -444,9 +444,11 @@ static CPAccessResult access_tdosa(CPUARMState *env, c= onst ARMCPRegInfo *ri, bool isread) { int el =3D arm_current_el(env); + bool mdcr_el2_tdosa =3D (env->cp15.mdcr_el2 & MDCR_TDOSA) || + (env->cp15.mdcr_el2 & MDCR_TDE) || + (env->cp15.hcr_el2 & HCR_TGE); =20 - if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TDOSA) - && !arm_is_secure_below_el3(env)) { + if (el < 2 && mdcr_el2_tdosa && !arm_is_secure_below_el3(env)) { return CP_ACCESS_TRAP_EL2; } if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDOSA)) { @@ -462,9 +464,11 @@ static CPAccessResult access_tdra(CPUARMState *env, co= nst ARMCPRegInfo *ri, bool isread) { int el =3D arm_current_el(env); + bool mdcr_el2_tdra =3D (env->cp15.mdcr_el2 & MDCR_TDRA) || + (env->cp15.mdcr_el2 & MDCR_TDE) || + (env->cp15.hcr_el2 & HCR_TGE); =20 - if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TDRA) - && !arm_is_secure_below_el3(env)) { + if (el < 2 && mdcr_el2_tdra && !arm_is_secure_below_el3(env)) { return CP_ACCESS_TRAP_EL2; } if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDA)) { @@ -480,9 +484,11 @@ static CPAccessResult access_tda(CPUARMState *env, con= st ARMCPRegInfo *ri, bool isread) { int el =3D arm_current_el(env); + bool mdcr_el2_tda =3D (env->cp15.mdcr_el2 & MDCR_TDA) || + (env->cp15.mdcr_el2 & MDCR_TDE) || + (env->cp15.hcr_el2 & HCR_TGE); =20 - if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TDA) - && !arm_is_secure_below_el3(env)) { + if (el < 2 && mdcr_el2_tda && !arm_is_secure_below_el3(env)) { return CP_ACCESS_TRAP_EL2; } if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDA)) { --=20 2.17.1 From nobody Wed Nov 5 02:34:55 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1532433954937697.0899688195478; Tue, 24 Jul 2018 05:05:54 -0700 (PDT) Received: from localhost ([::1]:39781 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fhw4f-0004W8-QK for importer@patchew.org; Tue, 24 Jul 2018 08:05:53 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52137) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fhvyw-0008A6-Cx for qemu-devel@nongnu.org; Tue, 24 Jul 2018 07:59:59 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fhvyv-00037S-Ii for qemu-devel@nongnu.org; Tue, 24 Jul 2018 07:59:58 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:43714) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fhvyt-00034o-9d; Tue, 24 Jul 2018 07:59:55 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fhvyr-0008Pm-QK; Tue, 24 Jul 2018 12:59:53 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 24 Jul 2018 12:59:48 +0100 Message-Id: <20180724115950.17316-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180724115950.17316-1-peter.maydell@linaro.org> References: <20180724115950.17316-1-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH 3/5] target/arm: Honour HCR_EL2.TGE when raising synchronous exceptions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Whene we raise a synchronous exception, if HCR_EL2.TGE is set then exceptions targeting NS EL1 must be redirected to EL2. Implement this in raise_exception() -- all synchronous exceptions go through this function. (Asynchronous exceptions go via arm_cpu_exec_interrupt(), which already honours HCR_EL2.TGE when it determines the target EL in arm_phys_excp_target_el().) Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/op_helper.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index f728f25e4bf..d550978b5b9 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -33,6 +33,20 @@ static void raise_exception(CPUARMState *env, uint32_t e= xcp, { CPUState *cs =3D CPU(arm_env_get_cpu(env)); =20 + if ((env->cp15.hcr_el2 & HCR_TGE) && + target_el =3D=3D 1 && !arm_is_secure(env)) { + /* + * Redirect NS EL1 exceptions to NS EL2. These are reported with + * their original syndrome register value, with the exception of + * SIMD/FP access traps, which are reported as uncategorized + * (see DDI0478C.a D1.10.4) + */ + target_el =3D 2; + if (syndrome >> ARM_EL_EC_SHIFT =3D=3D EC_ADVSIMDFPACCESSTRAP) { + syndrome =3D syn_uncategorized(); + } + } + assert(!excp_is_internal(excp)); cs->exception_index =3D excp; env->exception.syndrome =3D syndrome; --=20 2.17.1 From nobody Wed Nov 5 02:34:55 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1532434041349935.6979811775345; Tue, 24 Jul 2018 05:07:21 -0700 (PDT) Received: from localhost ([::1]:39787 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fhw62-0005gj-M6 for importer@patchew.org; Tue, 24 Jul 2018 08:07:18 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52191) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fhvyy-0008Ek-KB for qemu-devel@nongnu.org; Tue, 24 Jul 2018 08:00:10 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fhvyx-0003AI-9p for qemu-devel@nongnu.org; Tue, 24 Jul 2018 08:00:00 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:43722) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fhvyt-00035b-KV; Tue, 24 Jul 2018 07:59:55 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fhvys-0008QE-F9; Tue, 24 Jul 2018 12:59:54 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 24 Jul 2018 12:59:49 +0100 Message-Id: <20180724115950.17316-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180724115950.17316-1-peter.maydell@linaro.org> References: <20180724115950.17316-1-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH 4/5] target/arm: Provide accessor functions for HCR_EL2.{IMO, FMO, AMO} X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The IMO, FMO and AMO bits in HCR_EL2 are defined to "behave as 1 for all purposes other than direct reads" if HCR_EL2.TGE is set and HCR_EL2.E2H is 0, and to "behave as 0 for all purposes other than direct reads" if HCR_EL2.TGE is set and HRC_EL2.E2H is 1. To avoid having to check E2H and TGE everywhere where we test IMO and FMO, provide accessors arm_hcr_el2_imo(), arm_hcr_el2_fmo()and arm_hcr_el2_amo(). We don't implement ARMv8.1-VHE yet, so the E2H case will never be true, but we include the logic to save effort when we eventually do get to that. (Note that in several of these callsites the change doesn't actually make a difference as either the callsite is handling TGE specially anyway, or the CPU can't get into that situation with TGE set; we change everywhere for consistency.) Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu.h | 64 +++++++++++++++++++++++++++++++++++---- hw/intc/arm_gicv3_cpuif.c | 19 ++++++------ target/arm/helper.c | 6 ++-- 3 files changed, 71 insertions(+), 18 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index efb2a8d3f3d..4289c33ef4c 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1229,6 +1229,12 @@ static inline void xpsr_write(CPUARMState *env, uint= 32_t val, uint32_t mask) #define HCR_RW (1ULL << 31) #define HCR_CD (1ULL << 32) #define HCR_ID (1ULL << 33) +#define HCR_E2H (1ULL << 34) +/* + * When we actually implement ARMv8.1-VHE we should add HCR_E2H to + * HCR_MASK and then clear it again if the feature bit is not set in + * hcr_write(). + */ #define HCR_MASK ((1ULL << 34) - 1) =20 #define SCR_NS (1U << 0) @@ -2234,6 +2240,54 @@ bool write_cpustate_to_list(ARMCPU *cpu); # define TARGET_VIRT_ADDR_SPACE_BITS 32 #endif =20 +/** + * arm_hcr_el2_imo(): Return the effective value of HCR_EL2.IMO. + * Depending on the values of HCR_EL2.E2H and TGE, this may be + * "behaves as 1 for all purposes other than direct read/write" or + * "behaves as 0 for all purposes other than direct read/write" + */ +static inline bool arm_hcr_el2_imo(CPUARMState *env) +{ + switch (env->cp15.hcr_el2 & (HCR_TGE | HCR_E2H)) { + case HCR_TGE: + return true; + case HCR_TGE | HCR_E2H: + return false; + default: + return env->cp15.hcr_el2 & HCR_IMO; + } +} + +/** + * arm_hcr_el2_fmo(): Return the effective value of HCR_EL2.FMO. + */ +static inline bool arm_hcr_el2_fmo(CPUARMState *env) +{ + switch (env->cp15.hcr_el2 & (HCR_TGE | HCR_E2H)) { + case HCR_TGE: + return true; + case HCR_TGE | HCR_E2H: + return false; + default: + return env->cp15.hcr_el2 & HCR_FMO; + } +} + +/** + * arm_hcr_el2_amo(): Return the effective value of HCR_EL2.AMO. + */ +static inline bool arm_hcr_el2_amo(CPUARMState *env) +{ + switch (env->cp15.hcr_el2 & (HCR_TGE | HCR_E2H)) { + case HCR_TGE: + return true; + case HCR_TGE | HCR_E2H: + return false; + default: + return env->cp15.hcr_el2 & HCR_AMO; + } +} + static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx, unsigned int target_el) { @@ -2261,15 +2315,13 @@ static inline bool arm_excp_unmasked(CPUState *cs, = unsigned int excp_idx, break; =20 case EXCP_VFIQ: - if (secure || !(env->cp15.hcr_el2 & HCR_FMO) - || (env->cp15.hcr_el2 & HCR_TGE)) { + if (secure || !arm_hcr_el2_fmo(env) || (env->cp15.hcr_el2 & HCR_TG= E)) { /* VFIQs are only taken when hypervized and non-secure. */ return false; } return !(env->daif & PSTATE_F); case EXCP_VIRQ: - if (secure || !(env->cp15.hcr_el2 & HCR_IMO) - || (env->cp15.hcr_el2 & HCR_TGE)) { + if (secure || !arm_hcr_el2_imo(env) || (env->cp15.hcr_el2 & HCR_TG= E)) { /* VIRQs are only taken when hypervized and non-secure. */ return false; } @@ -2308,7 +2360,7 @@ static inline bool arm_excp_unmasked(CPUState *cs, un= signed int excp_idx, * to the CPSR.F setting otherwise we further assess the s= tate * below. */ - hcr =3D (env->cp15.hcr_el2 & HCR_FMO); + hcr =3D arm_hcr_el2_fmo(env); scr =3D (env->cp15.scr_el3 & SCR_FIQ); =20 /* When EL3 is 32-bit, the SCR.FW bit controls whether the @@ -2325,7 +2377,7 @@ static inline bool arm_excp_unmasked(CPUState *cs, un= signed int excp_idx, * when setting the target EL, so it does not have a furth= er * affect here. */ - hcr =3D (env->cp15.hcr_el2 & HCR_IMO); + hcr =3D arm_hcr_el2_imo(env); scr =3D false; break; default: diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c index 2a60568d82c..068a8e8e9b9 100644 --- a/hw/intc/arm_gicv3_cpuif.c +++ b/hw/intc/arm_gicv3_cpuif.c @@ -85,7 +85,10 @@ static bool icv_access(CPUARMState *env, int hcr_flags) * * access if NS EL1 and either IMO or FMO =3D=3D 1: * CTLR, DIR, PMR, RPR */ - return (env->cp15.hcr_el2 & hcr_flags) && arm_current_el(env) =3D=3D 1 + bool flagmatch =3D ((hcr_flags & HCR_IMO) && arm_hcr_el2_imo(env)) || + ((hcr_flags & HCR_FMO) && arm_hcr_el2_fmo(env)); + + return flagmatch && arm_current_el(env) =3D=3D 1 && !arm_is_secure_below_el3(env); } =20 @@ -1549,8 +1552,8 @@ static void icc_dir_write(CPUARMState *env, const ARM= CPRegInfo *ri, /* No need to include !IsSecure in route_*_to_el2 as it's only * tested in cases where we know !IsSecure is true. */ - route_fiq_to_el2 =3D env->cp15.hcr_el2 & HCR_FMO; - route_irq_to_el2 =3D env->cp15.hcr_el2 & HCR_IMO; + route_fiq_to_el2 =3D arm_hcr_el2_fmo(env); + route_irq_to_el2 =3D arm_hcr_el2_imo(env); =20 switch (arm_current_el(env)) { case 3: @@ -1893,7 +1896,7 @@ static CPAccessResult gicv3_irqfiq_access(CPUARMState= *env, switch (el) { case 1: if (arm_is_secure_below_el3(env) || - ((env->cp15.hcr_el2 & (HCR_IMO | HCR_FMO)) =3D=3D 0)) { + (arm_hcr_el2_imo(env) =3D=3D 0 && arm_hcr_el2_fmo(env) =3D= =3D 0)) { r =3D CP_ACCESS_TRAP_EL3; } break; @@ -1933,7 +1936,7 @@ static CPAccessResult gicv3_dir_access(CPUARMState *e= nv, static CPAccessResult gicv3_sgi_access(CPUARMState *env, const ARMCPRegInfo *ri, bool isread) { - if ((env->cp15.hcr_el2 & (HCR_IMO | HCR_FMO)) && + if ((arm_hcr_el2_imo(env) || arm_hcr_el2_fmo(env)) && arm_current_el(env) =3D=3D 1 && !arm_is_secure_below_el3(env)) { /* Takes priority over a possible EL3 trap */ return CP_ACCESS_TRAP_EL2; @@ -1958,8 +1961,7 @@ static CPAccessResult gicv3_fiq_access(CPUARMState *e= nv, if (env->cp15.scr_el3 & SCR_FIQ) { switch (el) { case 1: - if (arm_is_secure_below_el3(env) || - ((env->cp15.hcr_el2 & HCR_FMO) =3D=3D 0)) { + if (arm_is_secure_below_el3(env) || !arm_hcr_el2_fmo(env)) { r =3D CP_ACCESS_TRAP_EL3; } break; @@ -1998,8 +2000,7 @@ static CPAccessResult gicv3_irq_access(CPUARMState *e= nv, if (env->cp15.scr_el3 & SCR_IRQ) { switch (el) { case 1: - if (arm_is_secure_below_el3(env) || - ((env->cp15.hcr_el2 & HCR_IMO) =3D=3D 0)) { + if (arm_is_secure_below_el3(env) || !arm_hcr_el2_imo(env)) { r =3D CP_ACCESS_TRAP_EL3; } break; diff --git a/target/arm/helper.c b/target/arm/helper.c index e2930e99388..699189ebd7b 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6342,15 +6342,15 @@ uint32_t arm_phys_excp_target_el(CPUState *cs, uint= 32_t excp_idx, switch (excp_idx) { case EXCP_IRQ: scr =3D ((env->cp15.scr_el3 & SCR_IRQ) =3D=3D SCR_IRQ); - hcr =3D ((env->cp15.hcr_el2 & HCR_IMO) =3D=3D HCR_IMO); + hcr =3D arm_hcr_el2_imo(env); break; case EXCP_FIQ: scr =3D ((env->cp15.scr_el3 & SCR_FIQ) =3D=3D SCR_FIQ); - hcr =3D ((env->cp15.hcr_el2 & HCR_FMO) =3D=3D HCR_FMO); + hcr =3D arm_hcr_el2_fmo(env); break; default: scr =3D ((env->cp15.scr_el3 & SCR_EA) =3D=3D SCR_EA); - hcr =3D ((env->cp15.hcr_el2 & HCR_AMO) =3D=3D HCR_AMO); + hcr =3D arm_hcr_el2_amo(env); break; }; =20 --=20 2.17.1 From nobody Wed Nov 5 02:34:55 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 153243377381285.94723768554263; Tue, 24 Jul 2018 05:02:53 -0700 (PDT) Received: from localhost ([::1]:39757 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fhw1k-0001vo-MX for importer@patchew.org; Tue, 24 Jul 2018 08:02:52 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52171) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fhvyx-0008Cw-Qe for qemu-devel@nongnu.org; Tue, 24 Jul 2018 08:00:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fhvyw-00039O-Vx for qemu-devel@nongnu.org; Tue, 24 Jul 2018 07:59:59 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:43722) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fhvyu-00035b-KO; Tue, 24 Jul 2018 07:59:56 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fhvyt-0008Qj-4e; Tue, 24 Jul 2018 12:59:55 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Tue, 24 Jul 2018 12:59:50 +0100 Message-Id: <20180724115950.17316-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180724115950.17316-1-peter.maydell@linaro.org> References: <20180724115950.17316-1-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH 5/5] target/arm: Treat SCTLR_EL1.M as if it were zero when HCR_EL2.TGE is set X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" One of the required effects of setting HCR_EL2.TGE is that when SCR_EL3.NS is 1 then SCTLR_EL1.M must behave as if it is zero for all purposes except direct reads. That is, it effectively disables the MMU for the NS EL0/EL1 translation regime. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index 699189ebd7b..efd258fdb59 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8402,6 +8402,14 @@ static inline bool regime_translation_disabled(CPUAR= MState *env, if (mmu_idx =3D=3D ARMMMUIdx_S2NS) { return (env->cp15.hcr_el2 & HCR_VM) =3D=3D 0; } + + if (env->cp15.hcr_el2 & HCR_TGE) { + /* TGE means that NS EL0/1 act as if SCTLR_EL1.M is zero */ + if (!regime_is_secure(env, mmu_idx) && regime_el(env, mmu_idx) =3D= =3D 1) { + return true; + } + } + return (regime_sctlr(env, mmu_idx) & SCTLR_M) =3D=3D 0; } =20 --=20 2.17.1