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X-Received-From: 2607:f8b0:4003:c06::241 Subject: [Qemu-devel] [PATCH 79/99] target/arm: Introduce and use read_fp_hreg X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Richard Henderson , qemu-stable@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: Richard Henderson Cc: qemu-stable@nongnu.org Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Tested-by: Alex Benn=C3=A9e Message-id: 20180512003217.9105-6-richard.henderson@linaro.org Signed-off-by: Peter Maydell (cherry picked from commit 3d99d931266eaeaf7e83703a53f32232cd6faad7) Signed-off-by: Michael Roth --- target/arm/translate-a64.c | 30 ++++++++++++++---------------- 1 file changed, 14 insertions(+), 16 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index c5be901b5f..bcb3b5c5e7 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -614,6 +614,14 @@ static TCGv_i32 read_fp_sreg(DisasContext *s, int reg) return v; } =20 +static TCGv_i32 read_fp_hreg(DisasContext *s, int reg) +{ + TCGv_i32 v =3D tcg_temp_new_i32(); + + tcg_gen_ld16u_i32(v, cpu_env, fp_reg_offset(s, reg, MO_16)); + return v; +} + /* Clear the bits above an N-bit vector, for N =3D (is_q ? 128 : 64). * If SVE is not enabled, then there are only 128 bits in the vector. */ @@ -4638,11 +4646,9 @@ static void disas_fp_csel(DisasContext *s, uint32_t = insn) static void handle_fp_1src_half(DisasContext *s, int opcode, int rd, int r= n) { TCGv_ptr fpst =3D NULL; - TCGv_i32 tcg_op =3D tcg_temp_new_i32(); + TCGv_i32 tcg_op =3D read_fp_hreg(s, rn); TCGv_i32 tcg_res =3D tcg_temp_new_i32(); =20 - read_vec_element_i32(s, tcg_op, rn, 0, MO_16); - switch (opcode) { case 0x0: /* FMOV */ tcg_gen_mov_i32(tcg_res, tcg_op); @@ -7538,13 +7544,10 @@ static void disas_simd_scalar_three_reg_diff(DisasC= ontext *s, uint32_t insn) tcg_temp_free_i64(tcg_op2); tcg_temp_free_i64(tcg_res); } else { - TCGv_i32 tcg_op1 =3D tcg_temp_new_i32(); - TCGv_i32 tcg_op2 =3D tcg_temp_new_i32(); + TCGv_i32 tcg_op1 =3D read_fp_hreg(s, rn); + TCGv_i32 tcg_op2 =3D read_fp_hreg(s, rm); TCGv_i64 tcg_res =3D tcg_temp_new_i64(); =20 - read_vec_element_i32(s, tcg_op1, rn, 0, MO_16); - read_vec_element_i32(s, tcg_op2, rm, 0, MO_16); - gen_helper_neon_mull_s16(tcg_res, tcg_op1, tcg_op2); gen_helper_neon_addl_saturate_s32(tcg_res, cpu_env, tcg_res, tcg_r= es); =20 @@ -8085,13 +8088,10 @@ static void disas_simd_scalar_three_reg_same_fp16(D= isasContext *s, =20 fpst =3D get_fpstatus_ptr(true); =20 - tcg_op1 =3D tcg_temp_new_i32(); - tcg_op2 =3D tcg_temp_new_i32(); + tcg_op1 =3D read_fp_hreg(s, rn); + tcg_op2 =3D read_fp_hreg(s, rm); tcg_res =3D tcg_temp_new_i32(); =20 - read_vec_element_i32(s, tcg_op1, rn, 0, MO_16); - read_vec_element_i32(s, tcg_op2, rm, 0, MO_16); - switch (fpopcode) { case 0x03: /* FMULX */ gen_helper_advsimd_mulxh(tcg_res, tcg_op1, tcg_op2, fpst); @@ -12010,11 +12010,9 @@ static void disas_simd_two_reg_misc_fp16(DisasCont= ext *s, uint32_t insn) } =20 if (is_scalar) { - TCGv_i32 tcg_op =3D tcg_temp_new_i32(); + TCGv_i32 tcg_op =3D read_fp_hreg(s, rn); TCGv_i32 tcg_res =3D tcg_temp_new_i32(); =20 - read_vec_element_i32(s, tcg_op, rn, 0, MO_16); - switch (fpop) { case 0x1a: /* FCVTNS */ case 0x1b: /* FCVTMS */ --=20 2.17.1