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[76.251.165.188]) by smtp.gmail.com with ESMTPSA id d191-v6sm11786229oig.16.2018.07.23.13.19.57 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 23 Jul 2018 13:19:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=G6JoazjMed40MVxyj1L+YCMC0uKoKnoH67yK7zwbZaE=; b=Z9k4faswsPaL+Q3hv0Qn0WsN3rRSV3u9I1JYoG9rIgagYoGIG+z75HmQb1WSOyyUHY 7RnHqBroImGxYOZkXikuChgl+I0cj+l8+qFnQhDbjQY5QTrYKKHaZRnRlv9ODceCGeyo 7CFh7pgbzAi5BkBkla0UPSJF4H+5nRkgtRYRTSFIUsKYwDYUwsomBJuVE4/x99HrBFa7 Td2L5b2zppM2nSo/x9u/qaluAWi7GxJfhKBGIdehAvO78InKXkPdhlv5x7vbkOxKUWmM OygGZtf+aAlN5TqONcIGLDpZt2eavLE3pfREpXnUIspMMSK1tkeW9A/ZZlCPmNf3Zfji Hz7Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=G6JoazjMed40MVxyj1L+YCMC0uKoKnoH67yK7zwbZaE=; b=gsX8eBwK2vyxFUMUqynWSRLM4gRVhyS/3VU2CAevApYQad/MynssAkBq5S+FIBQSEC aUNtn2rs4AzLJp9AsV83+5fwvXx6Jq3af6VFcM0PqbP6a6aGg9yonBY2Jw5IpCK5Cm9V 7vpvQ9yppe4DJTz9INIFXBv5BCHIy3ffQ1i65vO38Qb4FKRWfzGLUuyySq/kuH2zKo2W 2dVqgKnR+A3hc6S15HvMhhagzHF5XvkJs8gyVULXX/GtKPpRzr5E01XGUhg7nf4jZD6+ Kav3qHcbXV2I9EJZDyu8Lu++EJr4A5KRvefP18eSad0FjMs/u1S6JeFBQ7IKqxeD0OFJ FRdg== X-Gm-Message-State: AOUpUlE1ZvhmRXELf7X6E5qm+dWp3JtwaKt/SWn7Kwz9S06kR4xDQ81D vurSSBiSTO5oO9EuZOLPPKSGscCVxOQ= X-Google-Smtp-Source: AAOMgpf1zugu830ldBewTUNYskQiBdPoD1uj79O6iGnq4zn4FFK1q4jDP317N3AFM5yBsSRaghevlg== X-Received: by 2002:aca:f5d1:: with SMTP id t200-v6mr340273oih.12.1532377199227; Mon, 23 Jul 2018 13:19:59 -0700 (PDT) From: Michael Roth To: qemu-devel@nongnu.org Date: Mon, 23 Jul 2018 15:16:51 -0500 Message-Id: <20180723201748.25573-43-mdroth@linux.vnet.ibm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180723201748.25573-1-mdroth@linux.vnet.ibm.com> References: <20180723201748.25573-1-mdroth@linux.vnet.ibm.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4003:c06::22e Subject: [Qemu-devel] [PATCH 42/99] i386: define the 'ssbd' CPUID feature bit (CVE-2018-3639) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-stable@nongnu.org, Eduardo Habkost , Konrad Rzeszutek Wilk Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 From: Daniel P. Berrang=C3=A9 New microcode introduces the "Speculative Store Bypass Disable" CPUID feature bit. This needs to be exposed to guest OS to allow them to protect against CVE-2018-3639. Signed-off-by: Daniel P. Berrang=C3=A9 Reviewed-by: Konrad Rzeszutek Wilk Signed-off-by: Konrad Rzeszutek Wilk Message-Id: <20180521215424.13520-2-berrange@redhat.com> Signed-off-by: Eduardo Habkost (cherry picked from commit d19d1f965904a533998739698020ff4ee8a103da) Signed-off-by: Michael Roth --- target/i386/cpu.c | 2 +- target/i386/cpu.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index a20fe26573..2f5263e22f 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -510,7 +510,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS]= =3D { NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, "spec-ctrl", NULL, - NULL, NULL, NULL, NULL, + NULL, NULL, NULL, "ssbd", }, .cpuid_eax =3D 7, .cpuid_needs_ecx =3D true, .cpuid_ecx =3D 0, diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 1b219fafc4..970ab96e54 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -684,6 +684,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; #define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) /* AVX512 Neural Network Ins= tructions */ #define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) /* AVX512 Multiply Accumulat= ion Single Precision */ #define CPUID_7_0_EDX_SPEC_CTRL (1U << 26) /* Speculation Control */ +#define CPUID_7_0_EDX_SPEC_CTRL_SSBD (1U << 31) /* Speculative Store Bypa= ss Disable */ =20 #define KVM_HINTS_DEDICATED (1U << 0) =20 --=20 2.17.1