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[76.251.165.188]) by smtp.gmail.com with ESMTPSA id b3-v6sm6695291oiy.11.2018.07.23.13.19.45 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 23 Jul 2018 13:19:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=cbZSqxll6sILlfbTMUK4hT7XybHqrRpj11iWLCkq8MI=; b=gcAMrkwqaccdOUx8LlP3N1/CgC9r9doGG0MugCnHIZmOmykxySmBIEHe5SM7/nNS3w thdXe+l5h0PeM3n0gI2ErB2Z4EG619KkJ3xYi9ok/FdcYu8PoPbPqRalWJzB73WOYtk0 NeqnGrcvbOqHOxdsMK1qe34/VgstX5B1IpYh2QJZZlOypt68zYOz8x+Q5Bwu6SKCMdHN 3SyCTsYxcgWja1HhFI/Lb3SM3/jpHEvQwYQvjW9whh4moYA7u76FzLKVkJlLwKpuoSdo yjZKFoLk8WkX6V2td9oTNzcwrAzQvBYDqf0PhmYqMZGMzQjkYpAuoZCTS4ZhkG9mQoHN LaAg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=cbZSqxll6sILlfbTMUK4hT7XybHqrRpj11iWLCkq8MI=; b=fADbk1EuTIFYahsjMxt0YgsrdeOsjaVWyGMFOfORxrXl2PVVf/r/4inb9f2w5mcnvz W1ZLvCOEvXd0gyKX57SfV4KPptFTPhYQsuSOOghU/jY0gXgDR2143yGCX9IkKkCPQ7Ht rk1Ld/tO7SWvVNI8AgvcgqnCTIyczbnz3uAqhTLATBBh4VmH1kwIQ/c+rbZ1ePitvdGA k+4E4BJDTyXCazXXtodkfVnJ7PK/YKj5wVxzoJDJjVd/P5C7779XWBvQlT84Rsz3E066 87Esed0ohy0+RBnQRzp2R4bn4FjAYP8GSpl2SYJLeYK4pvw80Lj/SaIWfDnV+HRjPX5g qu6Q== X-Gm-Message-State: AOUpUlEYnJriZD8qhVR6y93zdAQGnBC+68iqSOQ95H1XdXFYFRMCbivL 9Jv6UYHAjrQi2xHHG01CayEy5V8SWfc= X-Google-Smtp-Source: AAOMgpfAu9il7yPUZdWVSaEYv3FY14pBquR4FTQ5EsTfw9hWfh/HCqodWYMyXXBj02dkdnGOA8d/RA== X-Received: by 2002:aca:e2c7:: with SMTP id z190-v6mr330749oig.262.1532377186821; Mon, 23 Jul 2018 13:19:46 -0700 (PDT) From: Michael Roth To: qemu-devel@nongnu.org Date: Mon, 23 Jul 2018 15:16:46 -0500 Message-Id: <20180723201748.25573-38-mdroth@linux.vnet.ibm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180723201748.25573-1-mdroth@linux.vnet.ibm.com> References: <20180723201748.25573-1-mdroth@linux.vnet.ibm.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4003:c06::242 Subject: [Qemu-devel] [PATCH 37/99] arm_gicv3_kvm: kvm_dist_get/put: skip the registers banked by GICR X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-stable@nongnu.org, Shannon Zhao Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Shannon Zhao While we skip the GIC_INTERNAL irqs, we don't change the register offset accordingly. This will overlap the GICR registers value and leave the last GIC_INTERNAL irq's registers out of update. Fix this by skipping the registers banked by GICR. Also for migration compatibility if the migration source (old version qemu) doesn't send gicd_no_migration_shift_bug =3D 1 to destination, then we shift the data of PPI to get the right data for SPI. Fixes: 367b9f527becdd20ddf116e17a3c0c2bbc486920 Cc: qemu-stable@nongnu.org Reviewed-by: Eric Auger Reviewed-by: Peter Maydell Signed-off-by: Shannon Zhao Message-id: 1527816987-16108-1-git-send-email-zhaoshenglong@huawei.com Signed-off-by: Peter Maydell (cherry picked from commit 910e204841954b95c051b2ee49ab0f5c735ff93c) Signed-off-by: Michael Roth --- hw/intc/arm_gicv3_common.c | 79 ++++++++++++++++++++++++++++++ hw/intc/arm_gicv3_kvm.c | 38 ++++++++++++++ include/hw/intc/arm_gicv3_common.h | 1 + 3 files changed, 118 insertions(+) diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c index 7b54d52376..864b7c6515 100644 --- a/hw/intc/arm_gicv3_common.c +++ b/hw/intc/arm_gicv3_common.c @@ -27,6 +27,7 @@ #include "hw/intc/arm_gicv3_common.h" #include "gicv3_internal.h" #include "hw/arm/linux-boot-if.h" +#include "sysemu/kvm.h" =20 static int gicv3_pre_save(void *opaque) { @@ -141,6 +142,79 @@ static const VMStateDescription vmstate_gicv3_cpu =3D { } }; =20 +static int gicv3_gicd_no_migration_shift_bug_pre_load(void *opaque) +{ + GICv3State *cs =3D opaque; + + /* + * The gicd_no_migration_shift_bug flag is used for migration compatibi= lity + * for old version QEMU which may have the GICD bmp shift bug under KVM= mode. + * Strictly, what we want to know is whether the migration source is us= ing + * KVM. Since we don't have any way to determine that, we look at wheth= er the + * destination is using KVM; this is close enough because for the older= QEMU + * versions with this bug KVM -> TCG migration didn't work anyway. If t= he + * source is a newer QEMU without this bug it will transmit the migrati= on + * subsection which sets the flag to true; otherwise it will remain set= to + * the value we select here. + */ + if (kvm_enabled()) { + cs->gicd_no_migration_shift_bug =3D false; + } + + return 0; +} + +static int gicv3_gicd_no_migration_shift_bug_post_load(void *opaque, + int version_id) +{ + GICv3State *cs =3D opaque; + + if (cs->gicd_no_migration_shift_bug) { + return 0; + } + + /* Older versions of QEMU had a bug in the handling of state save/rest= ore + * to the KVM GICv3: they got the offset in the bitmap arrays wrong, + * so that instead of the data for external interrupts 32 and up + * starting at bit position 32 in the bitmap, it started at bit + * position 64. If we're receiving data from a QEMU with that bug, + * we must move the data down into the right place. + */ + memmove(cs->group, (uint8_t *)cs->group + GIC_INTERNAL / 8, + sizeof(cs->group) - GIC_INTERNAL / 8); + memmove(cs->grpmod, (uint8_t *)cs->grpmod + GIC_INTERNAL / 8, + sizeof(cs->grpmod) - GIC_INTERNAL / 8); + memmove(cs->enabled, (uint8_t *)cs->enabled + GIC_INTERNAL / 8, + sizeof(cs->enabled) - GIC_INTERNAL / 8); + memmove(cs->pending, (uint8_t *)cs->pending + GIC_INTERNAL / 8, + sizeof(cs->pending) - GIC_INTERNAL / 8); + memmove(cs->active, (uint8_t *)cs->active + GIC_INTERNAL / 8, + sizeof(cs->active) - GIC_INTERNAL / 8); + memmove(cs->edge_trigger, (uint8_t *)cs->edge_trigger + GIC_INTERNAL /= 8, + sizeof(cs->edge_trigger) - GIC_INTERNAL / 8); + + /* + * While this new version QEMU doesn't have this kind of bug as we fix= it, + * so it needs to set the flag to true to indicate that and it's neces= sary + * for next migration to work from this new version QEMU. + */ + cs->gicd_no_migration_shift_bug =3D true; + + return 0; +} + +const VMStateDescription vmstate_gicv3_gicd_no_migration_shift_bug =3D { + .name =3D "arm_gicv3/gicd_no_migration_shift_bug", + .version_id =3D 1, + .minimum_version_id =3D 1, + .pre_load =3D gicv3_gicd_no_migration_shift_bug_pre_load, + .post_load =3D gicv3_gicd_no_migration_shift_bug_post_load, + .fields =3D (VMStateField[]) { + VMSTATE_BOOL(gicd_no_migration_shift_bug, GICv3State), + VMSTATE_END_OF_LIST() + } +}; + static const VMStateDescription vmstate_gicv3 =3D { .name =3D "arm_gicv3", .version_id =3D 1, @@ -165,6 +239,10 @@ static const VMStateDescription vmstate_gicv3 =3D { VMSTATE_STRUCT_VARRAY_POINTER_UINT32(cpu, GICv3State, num_cpu, vmstate_gicv3_cpu, GICv3CPUSt= ate), VMSTATE_END_OF_LIST() + }, + .subsections =3D (const VMStateDescription * []) { + &vmstate_gicv3_gicd_no_migration_shift_bug, + NULL } }; =20 @@ -364,6 +442,7 @@ static void arm_gicv3_common_reset(DeviceState *dev) gicv3_gicd_group_set(s, i); } } + s->gicd_no_migration_shift_bug =3D true; } =20 static void arm_gic_common_linux_init(ARMLinuxBootIf *obj, diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c index 3536795501..81cbd16817 100644 --- a/hw/intc/arm_gicv3_kvm.c +++ b/hw/intc/arm_gicv3_kvm.c @@ -164,6 +164,14 @@ static void kvm_dist_get_edge_trigger(GICv3State *s, u= int32_t offset, uint32_t reg; int irq; =20 + /* For the KVM GICv3, affinity routing is always enabled, and the firs= t 2 + * GICD_ICFGR registers are always RAZ/WI. The corresponding + * functionality is replaced by GICR_ICFGR. It doesn't need to sync + * them. So it should increase the offset to skip GIC_INTERNAL irqs. + * This matches the for_each_dist_irq_reg() macro which also skips the + * first GIC_INTERNAL irqs. + */ + offset +=3D (GIC_INTERNAL * 2) / 8; for_each_dist_irq_reg(irq, s->num_irq, 2) { kvm_gicd_access(s, offset, ®, false); reg =3D half_unshuffle32(reg >> 1); @@ -181,6 +189,14 @@ static void kvm_dist_put_edge_trigger(GICv3State *s, u= int32_t offset, uint32_t reg; int irq; =20 + /* For the KVM GICv3, affinity routing is always enabled, and the firs= t 2 + * GICD_ICFGR registers are always RAZ/WI. The corresponding + * functionality is replaced by GICR_ICFGR. It doesn't need to sync + * them. So it should increase the offset to skip GIC_INTERNAL irqs. + * This matches the for_each_dist_irq_reg() macro which also skips the + * first GIC_INTERNAL irqs. + */ + offset +=3D (GIC_INTERNAL * 2) / 8; for_each_dist_irq_reg(irq, s->num_irq, 2) { reg =3D *gic_bmp_ptr32(bmp, irq); if (irq % 32 !=3D 0) { @@ -222,6 +238,15 @@ static void kvm_dist_getbmp(GICv3State *s, uint32_t of= fset, uint32_t *bmp) uint32_t reg; int irq; =20 + /* For the KVM GICv3, affinity routing is always enabled, and the + * GICD_IGROUPR0/GICD_IGRPMODR0/GICD_ISENABLER0/GICD_ISPENDR0/ + * GICD_ISACTIVER0 registers are always RAZ/WI. The corresponding + * functionality is replaced by the GICR registers. It doesn't need to= sync + * them. So it should increase the offset to skip GIC_INTERNAL irqs. + * This matches the for_each_dist_irq_reg() macro which also skips the + * first GIC_INTERNAL irqs. + */ + offset +=3D (GIC_INTERNAL * 1) / 8; for_each_dist_irq_reg(irq, s->num_irq, 1) { kvm_gicd_access(s, offset, ®, false); *gic_bmp_ptr32(bmp, irq) =3D reg; @@ -235,6 +260,19 @@ static void kvm_dist_putbmp(GICv3State *s, uint32_t of= fset, uint32_t reg; int irq; =20 + /* For the KVM GICv3, affinity routing is always enabled, and the + * GICD_IGROUPR0/GICD_IGRPMODR0/GICD_ISENABLER0/GICD_ISPENDR0/ + * GICD_ISACTIVER0 registers are always RAZ/WI. The corresponding + * functionality is replaced by the GICR registers. It doesn't need to= sync + * them. So it should increase the offset and clroffset to skip GIC_IN= TERNAL + * irqs. This matches the for_each_dist_irq_reg() macro which also ski= ps the + * first GIC_INTERNAL irqs. + */ + offset +=3D (GIC_INTERNAL * 1) / 8; + if (clroffset !=3D 0) { + clroffset +=3D (GIC_INTERNAL * 1) / 8; + } + for_each_dist_irq_reg(irq, s->num_irq, 1) { /* If this bitmap is a set/clear register pair, first write to the * clear-reg to clear all bits before using the set-reg to write diff --git a/include/hw/intc/arm_gicv3_common.h b/include/hw/intc/arm_gicv3= _common.h index bccdfe17c6..d75b49d558 100644 --- a/include/hw/intc/arm_gicv3_common.h +++ b/include/hw/intc/arm_gicv3_common.h @@ -217,6 +217,7 @@ struct GICv3State { uint32_t revision; bool security_extn; bool irq_reset_nonsecure; + bool gicd_no_migration_shift_bug; =20 int dev_fd; /* kvm device fd if backed by kvm vgic support */ Error *migration_blocker; --=20 2.17.1