From nobody Sun Dec 14 02:07:28 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1532349576576379.45205443844145; Mon, 23 Jul 2018 05:39:36 -0700 (PDT) Received: from localhost ([::1]:34413 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fha7j-00082N-Ik for importer@patchew.org; Mon, 23 Jul 2018 08:39:35 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38857) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fha3X-0005LF-G0 for qemu-devel@nongnu.org; Mon, 23 Jul 2018 08:35:16 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fha3W-00068X-FW for qemu-devel@nongnu.org; Mon, 23 Jul 2018 08:35:15 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:43682) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fha3O-0005lh-V0; Mon, 23 Jul 2018 08:35:07 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fha3G-0007eT-KS; Mon, 23 Jul 2018 13:34:58 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Mon, 23 Jul 2018 13:34:57 +0100 Message-Id: <20180723123457.2038-1-peter.maydell@linaro.org> X-Mailer: git-send-email 2.17.1 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH] target/arm: Escalate to correct HardFault when AIRCR.BFHFNMINS is set X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" When we escalate a v8M exception to HardFault, if AIRCR.BFHFNMINNS is set then we need to decide whether it should become a secure HardFault or a nonsecure HardFault. We should always escalate to the same target security state as the original exception. The current code tries to test this using the 'secure' bool, which is not right because that flag indicates whether the target security state only for banked exceptions; the effect was that we were incorrectly escalating always-secure exceptions like SecureFault to a nonsecure HardFault. Fix this by defining, logging and using a new 'targets_secure' bool which tracks the condition we actually want. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/intc/armv7m_nvic.c | 8 ++++++-- hw/intc/trace-events | 2 +- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index bf92fe0972c..e160b02eab4 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -529,13 +529,17 @@ static void do_armv7m_nvic_set_pending(void *opaque, = int irq, bool secure, NVICState *s =3D (NVICState *)opaque; bool banked =3D exc_is_banked(irq); VecInfo *vec; + bool targets_secure; =20 assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq); assert(!secure || banked); =20 vec =3D (banked && secure) ? &s->sec_vectors[irq] : &s->vectors[irq]; =20 - trace_nvic_set_pending(irq, secure, derived, vec->enabled, vec->prio); + targets_secure =3D banked ? secure : exc_targets_secure(s, irq); + + trace_nvic_set_pending(irq, secure, targets_secure, + derived, vec->enabled, vec->prio); =20 if (derived) { /* Derived exceptions are always synchronous. */ @@ -615,7 +619,7 @@ static void do_armv7m_nvic_set_pending(void *opaque, in= t irq, bool secure, */ irq =3D ARMV7M_EXCP_HARD; if (arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY) && - (secure || + (targets_secure || !(s->cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK))) { vec =3D &s->sec_vectors[irq]; } else { diff --git a/hw/intc/trace-events b/hw/intc/trace-events index b6cb5e6048d..33e932fb918 100644 --- a/hw/intc/trace-events +++ b/hw/intc/trace-events @@ -177,7 +177,7 @@ nvic_set_prio(int irq, bool secure, uint8_t prio) "NVIC= set irq %d secure-bank % nvic_irq_update(int vectpending, int pendprio, int exception_prio, int lev= el) "NVIC vectpending %d pending prio %d exception_prio %d: setting irq lin= e to %d" nvic_escalate_prio(int irq, int irqprio, int runprio) "NVIC escalating irq= %d to HardFault: insufficient priority %d >=3D %d" nvic_escalate_disabled(int irq) "NVIC escalating irq %d to HardFault: disa= bled" -nvic_set_pending(int irq, bool secure, bool derived, int en, int prio) "NV= IC set pending irq %d secure-bank %d derived %d (enabled: %d priority %d)" +nvic_set_pending(int irq, bool secure, bool targets_secure, bool derived, = int en, int prio) "NVIC set pending irq %d secure-bank %d targets_secure %d= derived %d (enabled: %d priority %d)" nvic_clear_pending(int irq, bool secure, int en, int prio) "NVIC clear pen= ding irq %d secure-bank %d (enabled: %d priority %d)" nvic_set_pending_level(int irq) "NVIC set pending: irq %d higher prio than= vectpending: setting irq line to 1" nvic_acknowledge_irq(int irq, int prio) "NVIC acknowledge IRQ: %d now acti= ve (prio %d)" --=20 2.17.1