From nobody Sat Feb 7 06:39:25 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1532101474595304.64797614274926; Fri, 20 Jul 2018 08:44:34 -0700 (PDT) Received: from localhost ([::1]:48667 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fgXa5-00020q-Fe for importer@patchew.org; Fri, 20 Jul 2018 11:44:33 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57650) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fgXVh-0007Qs-Af for qemu-devel@nongnu.org; Fri, 20 Jul 2018 11:40:02 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fgXVg-0008Nk-EY for qemu-devel@nongnu.org; Fri, 20 Jul 2018 11:40:01 -0400 Received: from foss.arm.com ([217.140.101.70]:46194) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fgXVg-0008Mf-8Y for qemu-devel@nongnu.org; Fri, 20 Jul 2018 11:40:00 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 925E315A2; Fri, 20 Jul 2018 08:39:59 -0700 (PDT) Received: from e104803-lin.cambridge.arm.com (e104803-lin.cambridge.arm.com [10.1.206.130]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id EB9D13F5B3; Fri, 20 Jul 2018 08:39:57 -0700 (PDT) From: Andre Przywara To: Andrew Jones Date: Fri, 20 Jul 2018 16:39:42 +0100 Message-Id: <20180720153942.26821-5-andre.przywara@arm.com> X-Mailer: git-send-email 2.14.4 In-Reply-To: <20180720153942.26821-1-andre.przywara@arm.com> References: <20180720153942.26821-1-andre.przywara@arm.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 217.140.101.70 Subject: [Qemu-devel] [kvm-unit-tests PATCH v2 4/4] arm/arm64: GICv2: add GICD_ITARGETSR testing X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , kvm@vger.kernel.org, Marc Zyngier , Christoffer Dall , qemu-devel@nongnu.org, Eric Auger , kvmarm@lists.cs.columbia.edu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Some tests for the ITARGETS registers. Bits corresponding to non-existent CPUs must be RAZ/WI. These registers must be byte-accessible, also check that accesses beyond the implemented IRQ limit are actually read-as-zero/write-ignore. Signed-off-by: Andre Przywara Reviewed-by: Andrew Jones --- arm/gic.c | 43 +++++++++++++++++++++++++++++++++++++++++++ lib/arm/asm/gic.h | 1 + 2 files changed, 44 insertions(+) diff --git a/arm/gic.c b/arm/gic.c index 57a2995..ed5642e 100644 --- a/arm/gic.c +++ b/arm/gic.c @@ -431,6 +431,46 @@ static void test_priorities(int nr_irqs, void *priptr) writel(orig_prio, first_spi); } =20 +/* GICD_ITARGETSR is only used by GICv2. */ +static void test_targets(int nr_irqs) +{ + void *targetsptr =3D gicv2_dist_base() + GICD_ITARGETSR; + u32 orig_targets; + u32 cpu_mask; + u32 pattern, reg; + + orig_targets =3D readl(targetsptr + GIC_FIRST_SPI); + report_prefix_push("ITARGETSR"); + + cpu_mask =3D (1 << nr_cpus) - 1; + cpu_mask |=3D cpu_mask << 8; + cpu_mask |=3D cpu_mask << 16; + + /* Check that bits for non implemented CPUs are RAZ/WI. */ + if (nr_cpus < 8) { + writel(0xffffffff, targetsptr + GIC_FIRST_SPI); + report("bits for %d non-existent CPUs masked", + !(readl(targetsptr + GIC_FIRST_SPI) & ~cpu_mask), + 8 - nr_cpus); + } else { + report_skip("CPU masking (all CPUs implemented)"); + } + + report("accesses beyond limit RAZ/WI", + test_readonly_32(targetsptr + nr_irqs, true)); + + pattern =3D 0x0103020f; + writel(pattern, targetsptr + GIC_FIRST_SPI); + reg =3D readl(targetsptr + GIC_FIRST_SPI); + report("register content preserved (%08x =3D> %08x)", + reg =3D=3D (pattern & cpu_mask), pattern & cpu_mask, reg); + + /* The TARGETS registers are byte accessible. */ + test_byte_access(targetsptr + GIC_FIRST_SPI, pattern, cpu_mask); + + writel(orig_targets, targetsptr + GIC_FIRST_SPI); +} + static void gic_test_mmio(void) { u32 reg; @@ -467,6 +507,9 @@ static void gic_test_mmio(void) reg); =20 test_priorities(nr_irqs, gic_dist_base + GICD_IPRIORITYR); + + if (gic_version() =3D=3D 2) + test_targets(nr_irqs); } =20 int main(int argc, char **argv) diff --git a/lib/arm/asm/gic.h b/lib/arm/asm/gic.h index a469645..f6dfb90 100644 --- a/lib/arm/asm/gic.h +++ b/lib/arm/asm/gic.h @@ -20,6 +20,7 @@ #define GICD_ISACTIVER 0x0300 #define GICD_ICACTIVER 0x0380 #define GICD_IPRIORITYR 0x0400 +#define GICD_ITARGETSR 0x0800 #define GICD_SGIR 0x0f00 #define GICD_ICPIDR2 0x0fe8 =20 --=20 2.14.4