From nobody Sat Feb 7 06:39:32 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1532101475554594.9379447510194; Fri, 20 Jul 2018 08:44:35 -0700 (PDT) Received: from localhost ([::1]:48668 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fgXa6-00021g-Dl for importer@patchew.org; Fri, 20 Jul 2018 11:44:34 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57638) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fgXVf-0007PY-H2 for qemu-devel@nongnu.org; Fri, 20 Jul 2018 11:40:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fgXVe-0008KV-Gi for qemu-devel@nongnu.org; Fri, 20 Jul 2018 11:39:59 -0400 Received: from foss.arm.com ([217.140.101.70]:46176) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fgXVe-0008JP-Ap for qemu-devel@nongnu.org; Fri, 20 Jul 2018 11:39:58 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id AE73980D; Fri, 20 Jul 2018 08:39:57 -0700 (PDT) Received: from e104803-lin.cambridge.arm.com (e104803-lin.cambridge.arm.com [10.1.206.130]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 130CE3F5B3; Fri, 20 Jul 2018 08:39:55 -0700 (PDT) From: Andre Przywara To: Andrew Jones Date: Fri, 20 Jul 2018 16:39:41 +0100 Message-Id: <20180720153942.26821-4-andre.przywara@arm.com> X-Mailer: git-send-email 2.14.4 In-Reply-To: <20180720153942.26821-1-andre.przywara@arm.com> References: <20180720153942.26821-1-andre.przywara@arm.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 217.140.101.70 Subject: [Qemu-devel] [kvm-unit-tests PATCH v2 3/4] arm/arm64: GICv2: add GICD_IPRIORITYR testing X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , kvm@vger.kernel.org, Marc Zyngier , Christoffer Dall , qemu-devel@nongnu.org, Eric Auger , kvmarm@lists.cs.columbia.edu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Some tests for the IPRIORITY registers. The significant number of bits is IMPLEMENTATION DEFINED, but should be the same for every IRQ. Also these registers must be byte-accessible. Check that accesses beyond the implemented IRQ limit are actually read-as-zero/write-ignore. Signed-off-by: Andre Przywara Reviewed-by: Andrew Jones --- arm/gic.c | 79 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 79 insertions(+) diff --git a/arm/gic.c b/arm/gic.c index 23cb9a4..57a2995 100644 --- a/arm/gic.c +++ b/arm/gic.c @@ -354,6 +354,83 @@ static void test_typer_v2(uint32_t reg) nr_gic_cpus); } =20 +#define BYTE(reg32, byte) (((reg32) >> ((byte) * 8)) & 0xff) +#define REPLACE_BYTE(reg32, byte, new) (((reg32) & ~(0xff << ((byte) * 8))= ) |\ + ((new) << ((byte) * 8))) + +/* + * Some registers are byte accessible, do a byte-wide read and write of kn= own + * content to check for this. + * Apply a @mask to cater for special register properties. + * @pattern contains the value already in the register. + */ +static void test_byte_access(void *base_addr, u32 pattern, u32 mask) +{ + u32 reg =3D readb(base_addr + 1); + + report("byte reads successful (0x%08x =3D> 0x%02x)", + reg =3D=3D (BYTE(pattern, 1) & (mask >> 8)), + pattern & mask, reg); + + pattern =3D REPLACE_BYTE(pattern, 2, 0x1f); + writeb(BYTE(pattern, 2), base_addr + 2); + reg =3D readl(base_addr); + report("byte writes successful (0x%02x =3D> 0x%08x)", + reg =3D=3D (pattern & mask), BYTE(pattern, 2), reg); +} + +static void test_priorities(int nr_irqs, void *priptr) +{ + u32 orig_prio, reg, pri_bits; + u32 pri_mask, pattern; + void *first_spi =3D priptr + GIC_FIRST_SPI; + + orig_prio =3D readl(first_spi); + report_prefix_push("IPRIORITYR"); + + /* + * Determine implemented number of priority bits by writing all 1's + * and checking the number of cleared bits in the value read back. + */ + writel(0xffffffff, first_spi); + pri_mask =3D readl(first_spi); + + reg =3D ~pri_mask; + report("consistent priority masking (0x%08x)", + (((reg >> 16) =3D=3D (reg & 0xffff)) && + ((reg & 0xff) =3D=3D ((reg >> 8) & 0xff))), pri_mask); + + reg =3D reg & 0xff; + for (pri_bits =3D 8; reg & 1; reg >>=3D 1, pri_bits--) + ; + report("implements at least 4 priority bits (%d)", + pri_bits >=3D 4, pri_bits); + + pattern =3D 0; + writel(pattern, first_spi); + report("clearing priorities", readl(first_spi) =3D=3D pattern); + + /* setting all priorities to their max valus was tested above */ + + report("accesses beyond limit RAZ/WI", + test_readonly_32(priptr + nr_irqs, true)); + + writel(pattern, priptr + nr_irqs - 4); + report("accessing last SPIs", + readl(priptr + nr_irqs - 4) =3D=3D (pattern & pri_mask)); + + pattern =3D 0xff7fbf3f; + writel(pattern, first_spi); + report("priorities are preserved", + readl(first_spi) =3D=3D (pattern & pri_mask)); + + /* The PRIORITY registers are byte accessible. */ + test_byte_access(first_spi, pattern, pri_mask); + + report_prefix_pop(); + writel(orig_prio, first_spi); +} + static void gic_test_mmio(void) { u32 reg; @@ -388,6 +465,8 @@ static void gic_test_mmio(void) report("ICPIDR2 is read-only (0x%08x)", test_readonly_32(idreg, false), reg); + + test_priorities(nr_irqs, gic_dist_base + GICD_IPRIORITYR); } =20 int main(int argc, char **argv) --=20 2.14.4