From nobody Thu May 2 01:18:54 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1532101340200959.0468332032218; Fri, 20 Jul 2018 08:42:20 -0700 (PDT) Received: from localhost ([::1]:48655 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fgXXn-0000DZ-Cn for importer@patchew.org; Fri, 20 Jul 2018 11:42:11 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57607) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fgXVd-0007PW-8Q for qemu-devel@nongnu.org; Fri, 20 Jul 2018 11:39:59 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fgXVa-0008Fn-Hw for qemu-devel@nongnu.org; Fri, 20 Jul 2018 11:39:57 -0400 Received: from foss.arm.com ([217.140.101.70]:46148) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fgXVa-0008Em-BK for qemu-devel@nongnu.org; Fri, 20 Jul 2018 11:39:54 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C1FC415A2; Fri, 20 Jul 2018 08:39:53 -0700 (PDT) Received: from e104803-lin.cambridge.arm.com (e104803-lin.cambridge.arm.com [10.1.206.130]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 263D03F5B3; Fri, 20 Jul 2018 08:39:52 -0700 (PDT) From: Andre Przywara To: Andrew Jones Date: Fri, 20 Jul 2018 16:39:39 +0100 Message-Id: <20180720153942.26821-2-andre.przywara@arm.com> X-Mailer: git-send-email 2.14.4 In-Reply-To: <20180720153942.26821-1-andre.przywara@arm.com> References: <20180720153942.26821-1-andre.przywara@arm.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 217.140.101.70 Subject: [Qemu-devel] [kvm-unit-tests PATCH v2 1/4] mark exit() and abort() as non-returning functions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , kvm@vger.kernel.org, Marc Zyngier , Christoffer Dall , qemu-devel@nongnu.org, Eric Auger , kvmarm@lists.cs.columbia.edu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" exit() and abort() are functions that never return, and (at least) GCC has an attribute to flag those functions accordingly. This allows the compiler to do further optimizations and to omit various warnings about uninitialized variables, for instance. Since the actual "play-dead" function is in (inline) assembly, the compiler does not recognize its fatal nature, so help it with the __builtin_unreachable() hint. Flag the prototypes of our fatal functions accordingly. Signed-off-by: Andre Przywara Reviewed-by: Andrew Jones --- lib/arm/io.c | 1 + lib/libcflat.h | 7 ++++--- lib/powerpc/io.c | 1 + lib/x86/io.c | 1 + 4 files changed, 7 insertions(+), 3 deletions(-) diff --git a/lib/arm/io.c b/lib/arm/io.c index 603456f..d2c1a07 100644 --- a/lib/arm/io.c +++ b/lib/arm/io.c @@ -83,4 +83,5 @@ void exit(int code) { chr_testdev_exit(code); halt(code); + __builtin_unreachable(); } diff --git a/lib/libcflat.h b/lib/libcflat.h index cc56553..7529958 100644 --- a/lib/libcflat.h +++ b/lib/libcflat.h @@ -84,8 +84,8 @@ typedef u64 phys_addr_t; extern void puts(const char *s); extern int __getchar(void); extern int getchar(void); -extern void exit(int code); -extern void abort(void); +extern void exit(int code) __attribute__((noreturn)); +extern void abort(void) __attribute__((noreturn)); extern long atol(const char *ptr); extern char *getenv(const char *name); =20 @@ -107,7 +107,8 @@ extern void report(const char *msg_fmt, bool pass, ...) extern void report_xfail(const char *msg_fmt, bool xfail, bool pass, ...) __attribute__((format(printf, 1, 4))); extern void report_abort(const char *msg_fmt, ...) - __attribute__((format(printf, 1, 2))); + __attribute__((format(printf, 1, 2))) + __attribute__((noreturn)); extern void report_skip(const char *msg_fmt, ...) __attribute__((format(printf, 1, 2))); extern void report_info(const char *msg_fmt, ...) diff --git a/lib/powerpc/io.c b/lib/powerpc/io.c index 915e12e..217eb07 100644 --- a/lib/powerpc/io.c +++ b/lib/powerpc/io.c @@ -35,4 +35,5 @@ void exit(int code) printf("\nEXIT: STATUS=3D%d\n", ((code) << 1) | 1); rtas_power_off(); halt(code); + __builtin_unreachable(); } diff --git a/lib/x86/io.c b/lib/x86/io.c index 7e1c16d..057f579 100644 --- a/lib/x86/io.c +++ b/lib/x86/io.c @@ -82,6 +82,7 @@ void exit(int code) #else asm volatile("out %0, %1" : : "a"(code), "d"((short)0xf4)); #endif + __builtin_unreachable(); } =20 void __iomem *ioremap(phys_addr_t phys_addr, size_t size) --=20 2.14.4 From nobody Thu May 2 01:18:54 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1532101333703555.2610854902665; Fri, 20 Jul 2018 08:42:13 -0700 (PDT) Received: from localhost ([::1]:48656 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fgXXo-0000Ek-Mh for importer@patchew.org; Fri, 20 Jul 2018 11:42:12 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57621) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fgXVd-0007PX-Qp for qemu-devel@nongnu.org; Fri, 20 Jul 2018 11:39:59 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fgXVc-0008I6-N3 for qemu-devel@nongnu.org; Fri, 20 Jul 2018 11:39:57 -0400 Received: from foss.arm.com ([217.140.101.70]:46160) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fgXVc-0008HA-FK for qemu-devel@nongnu.org; Fri, 20 Jul 2018 11:39:56 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C9B4315A2; Fri, 20 Jul 2018 08:39:55 -0700 (PDT) Received: from e104803-lin.cambridge.arm.com (e104803-lin.cambridge.arm.com [10.1.206.130]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 0B0683F5B3; Fri, 20 Jul 2018 08:39:53 -0700 (PDT) From: Andre Przywara To: Andrew Jones Date: Fri, 20 Jul 2018 16:39:40 +0100 Message-Id: <20180720153942.26821-3-andre.przywara@arm.com> X-Mailer: git-send-email 2.14.4 In-Reply-To: <20180720153942.26821-1-andre.przywara@arm.com> References: <20180720153942.26821-1-andre.przywara@arm.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 217.140.101.70 Subject: [Qemu-devel] [kvm-unit-tests PATCH v2 2/4] arm/arm64: GIC: basic GICv2 MMIO tests X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , kvm@vger.kernel.org, Marc Zyngier , Christoffer Dall , qemu-devel@nongnu.org, Eric Auger , kvmarm@lists.cs.columbia.edu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This adds an MMIO subtest to the GIC test. It accesses some generic GICv2 registers and does some sanity tests, like checking for some of them being read-only. Signed-off-by: Andre Przywara Reviewed-by: Andrew Jones --- arm/gic.c | 91 +++++++++++++++++++++++++++++++++++++++++++++++++++= ++++ arm/unittests.cfg | 18 +++++++++++ lib/arm/asm/gic.h | 4 +++ 3 files changed, 113 insertions(+) diff --git a/arm/gic.c b/arm/gic.c index 5dd958e..23cb9a4 100644 --- a/arm/gic.c +++ b/arm/gic.c @@ -3,6 +3,7 @@ * * GICv2 * + test sending/receiving IPIs + * + MMIO access tests * GICv3 * + test sending/receiving IPIs * @@ -303,6 +304,92 @@ static void run_active_clear_test(void) report_prefix_pop(); } =20 +static bool test_ro_pattern_32(void *address, u32 pattern, u32 orig) +{ + u32 reg; + + writel(pattern, address); + reg =3D readl(address); + + if (reg !=3D orig) + writel(orig, address); + + return reg =3D=3D orig; +} + +static bool test_readonly_32(void *address, bool razwi) +{ + u32 orig, pattern; + + orig =3D readl(address); + if (razwi && orig) + return false; + + pattern =3D 0xffffffff; + if (orig !=3D pattern) { + if (!test_ro_pattern_32(address, pattern, orig)) + return false; + } + + pattern =3D 0xa5a55a5a; + if (orig !=3D pattern) { + if (!test_ro_pattern_32(address, pattern, orig)) + return false; + } + + pattern =3D 0; + if (orig !=3D pattern) { + if (!test_ro_pattern_32(address, pattern, orig)) + return false; + } + + return true; +} + +static void test_typer_v2(uint32_t reg) +{ + int nr_gic_cpus =3D ((reg >> 5) & 0x7) + 1; + + report("all %d CPUs have interrupts", nr_cpus =3D=3D nr_gic_cpus, + nr_gic_cpus); +} + +static void gic_test_mmio(void) +{ + u32 reg; + int nr_irqs; + void *gic_dist_base, *idreg; + + switch(gic_version()) { + case 0x2: + gic_dist_base =3D gicv2_dist_base(); + idreg =3D gic_dist_base + GICD_ICPIDR2; + break; + case 0x3: + report_abort("GICv3 MMIO tests NYI"); + default: + report_abort("GIC version %d not supported", gic_version()); + } + + reg =3D readl(gic_dist_base + GICD_TYPER); + nr_irqs =3D GICD_TYPER_IRQS(reg); + report_info("number of implemented SPIs: %d", nr_irqs - GIC_FIRST_SPI); + + test_typer_v2(reg); + + report_info("IIDR: 0x%08x", readl(gic_dist_base + GICD_IIDR)); + + report("GICD_TYPER is read-only", + test_readonly_32(gic_dist_base + GICD_TYPER, false)); + report("GICD_IIDR is read-only", + test_readonly_32(gic_dist_base + GICD_IIDR, false)); + + reg =3D readl(idreg); + report("ICPIDR2 is read-only (0x%08x)", + test_readonly_32(idreg, false), + reg); +} + int main(int argc, char **argv) { if (!gic_init()) { @@ -330,6 +417,10 @@ int main(int argc, char **argv) on_cpus(ipi_test, NULL); } else if (strcmp(argv[1], "active") =3D=3D 0) { run_active_clear_test(); + } else if (strcmp(argv[1], "mmio") =3D=3D 0) { + report_prefix_push(argv[1]); + gic_test_mmio(); + report_prefix_pop(); } else { report_abort("Unknown subtest '%s'", argv[1]); } diff --git a/arm/unittests.cfg b/arm/unittests.cfg index 44b98cf..7f3a321 100644 --- a/arm/unittests.cfg +++ b/arm/unittests.cfg @@ -86,6 +86,24 @@ smp =3D $((($MAX_SMP < 8)?$MAX_SMP:8)) extra_params =3D -machine gic-version=3D2 -append 'ipi' groups =3D gic =20 +[gicv2-mmio] +file =3D gic.flat +smp =3D $((($MAX_SMP < 8)?$MAX_SMP:8)) +extra_params =3D -machine gic-version=3D2 -append 'mmio' +groups =3D gic + +[gicv2-mmio-up] +file =3D gic.flat +smp =3D 1 +extra_params =3D -machine gic-version=3D2 -append 'mmio' +groups =3D gic + +[gicv2-mmio-3p] +file =3D gic.flat +smp =3D $((($MAX_SMP < 3)?$MAX_SMP:3)) +extra_params =3D -machine gic-version=3D2 -append 'mmio' +groups =3D gic + [gicv3-ipi] file =3D gic.flat smp =3D $MAX_SMP diff --git a/lib/arm/asm/gic.h b/lib/arm/asm/gic.h index 2eb4af8..a469645 100644 --- a/lib/arm/asm/gic.h +++ b/lib/arm/asm/gic.h @@ -6,10 +6,13 @@ #ifndef _ASMARM_GIC_H_ #define _ASMARM_GIC_H_ =20 +#define GIC_NR_PRIVATE_IRQS 32 +#define GIC_FIRST_SPI GIC_NR_PRIVATE_IRQS =20 /* Distributor registers */ #define GICD_CTLR 0x0000 #define GICD_TYPER 0x0004 +#define GICD_IIDR 0x0008 #define GICD_IGROUPR 0x0080 #define GICD_ISENABLER 0x0100 #define GICD_ISPENDR 0x0200 @@ -18,6 +21,7 @@ #define GICD_ICACTIVER 0x0380 #define GICD_IPRIORITYR 0x0400 #define GICD_SGIR 0x0f00 +#define GICD_ICPIDR2 0x0fe8 =20 #define GICD_TYPER_IRQS(typer) ((((typer) & 0x1f) + 1) * 32) #define GICD_INT_EN_SET_SGI 0x0000ffff --=20 2.14.4 From nobody Thu May 2 01:18:54 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1532101475554594.9379447510194; Fri, 20 Jul 2018 08:44:35 -0700 (PDT) Received: from localhost ([::1]:48668 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fgXa6-00021g-Dl for importer@patchew.org; Fri, 20 Jul 2018 11:44:34 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57638) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fgXVf-0007PY-H2 for qemu-devel@nongnu.org; Fri, 20 Jul 2018 11:40:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fgXVe-0008KV-Gi for qemu-devel@nongnu.org; Fri, 20 Jul 2018 11:39:59 -0400 Received: from foss.arm.com ([217.140.101.70]:46176) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fgXVe-0008JP-Ap for qemu-devel@nongnu.org; Fri, 20 Jul 2018 11:39:58 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id AE73980D; Fri, 20 Jul 2018 08:39:57 -0700 (PDT) Received: from e104803-lin.cambridge.arm.com (e104803-lin.cambridge.arm.com [10.1.206.130]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 130CE3F5B3; Fri, 20 Jul 2018 08:39:55 -0700 (PDT) From: Andre Przywara To: Andrew Jones Date: Fri, 20 Jul 2018 16:39:41 +0100 Message-Id: <20180720153942.26821-4-andre.przywara@arm.com> X-Mailer: git-send-email 2.14.4 In-Reply-To: <20180720153942.26821-1-andre.przywara@arm.com> References: <20180720153942.26821-1-andre.przywara@arm.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 217.140.101.70 Subject: [Qemu-devel] [kvm-unit-tests PATCH v2 3/4] arm/arm64: GICv2: add GICD_IPRIORITYR testing X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , kvm@vger.kernel.org, Marc Zyngier , Christoffer Dall , qemu-devel@nongnu.org, Eric Auger , kvmarm@lists.cs.columbia.edu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Some tests for the IPRIORITY registers. The significant number of bits is IMPLEMENTATION DEFINED, but should be the same for every IRQ. Also these registers must be byte-accessible. Check that accesses beyond the implemented IRQ limit are actually read-as-zero/write-ignore. Signed-off-by: Andre Przywara Reviewed-by: Andrew Jones --- arm/gic.c | 79 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 79 insertions(+) diff --git a/arm/gic.c b/arm/gic.c index 23cb9a4..57a2995 100644 --- a/arm/gic.c +++ b/arm/gic.c @@ -354,6 +354,83 @@ static void test_typer_v2(uint32_t reg) nr_gic_cpus); } =20 +#define BYTE(reg32, byte) (((reg32) >> ((byte) * 8)) & 0xff) +#define REPLACE_BYTE(reg32, byte, new) (((reg32) & ~(0xff << ((byte) * 8))= ) |\ + ((new) << ((byte) * 8))) + +/* + * Some registers are byte accessible, do a byte-wide read and write of kn= own + * content to check for this. + * Apply a @mask to cater for special register properties. + * @pattern contains the value already in the register. + */ +static void test_byte_access(void *base_addr, u32 pattern, u32 mask) +{ + u32 reg =3D readb(base_addr + 1); + + report("byte reads successful (0x%08x =3D> 0x%02x)", + reg =3D=3D (BYTE(pattern, 1) & (mask >> 8)), + pattern & mask, reg); + + pattern =3D REPLACE_BYTE(pattern, 2, 0x1f); + writeb(BYTE(pattern, 2), base_addr + 2); + reg =3D readl(base_addr); + report("byte writes successful (0x%02x =3D> 0x%08x)", + reg =3D=3D (pattern & mask), BYTE(pattern, 2), reg); +} + +static void test_priorities(int nr_irqs, void *priptr) +{ + u32 orig_prio, reg, pri_bits; + u32 pri_mask, pattern; + void *first_spi =3D priptr + GIC_FIRST_SPI; + + orig_prio =3D readl(first_spi); + report_prefix_push("IPRIORITYR"); + + /* + * Determine implemented number of priority bits by writing all 1's + * and checking the number of cleared bits in the value read back. + */ + writel(0xffffffff, first_spi); + pri_mask =3D readl(first_spi); + + reg =3D ~pri_mask; + report("consistent priority masking (0x%08x)", + (((reg >> 16) =3D=3D (reg & 0xffff)) && + ((reg & 0xff) =3D=3D ((reg >> 8) & 0xff))), pri_mask); + + reg =3D reg & 0xff; + for (pri_bits =3D 8; reg & 1; reg >>=3D 1, pri_bits--) + ; + report("implements at least 4 priority bits (%d)", + pri_bits >=3D 4, pri_bits); + + pattern =3D 0; + writel(pattern, first_spi); + report("clearing priorities", readl(first_spi) =3D=3D pattern); + + /* setting all priorities to their max valus was tested above */ + + report("accesses beyond limit RAZ/WI", + test_readonly_32(priptr + nr_irqs, true)); + + writel(pattern, priptr + nr_irqs - 4); + report("accessing last SPIs", + readl(priptr + nr_irqs - 4) =3D=3D (pattern & pri_mask)); + + pattern =3D 0xff7fbf3f; + writel(pattern, first_spi); + report("priorities are preserved", + readl(first_spi) =3D=3D (pattern & pri_mask)); + + /* The PRIORITY registers are byte accessible. */ + test_byte_access(first_spi, pattern, pri_mask); + + report_prefix_pop(); + writel(orig_prio, first_spi); +} + static void gic_test_mmio(void) { u32 reg; @@ -388,6 +465,8 @@ static void gic_test_mmio(void) report("ICPIDR2 is read-only (0x%08x)", test_readonly_32(idreg, false), reg); + + test_priorities(nr_irqs, gic_dist_base + GICD_IPRIORITYR); } =20 int main(int argc, char **argv) --=20 2.14.4 From nobody Thu May 2 01:18:54 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1532101474595304.64797614274926; Fri, 20 Jul 2018 08:44:34 -0700 (PDT) Received: from localhost ([::1]:48667 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fgXa5-00020q-Fe for importer@patchew.org; Fri, 20 Jul 2018 11:44:33 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57650) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fgXVh-0007Qs-Af for qemu-devel@nongnu.org; Fri, 20 Jul 2018 11:40:02 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fgXVg-0008Nk-EY for qemu-devel@nongnu.org; Fri, 20 Jul 2018 11:40:01 -0400 Received: from foss.arm.com ([217.140.101.70]:46194) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fgXVg-0008Mf-8Y for qemu-devel@nongnu.org; Fri, 20 Jul 2018 11:40:00 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 925E315A2; Fri, 20 Jul 2018 08:39:59 -0700 (PDT) Received: from e104803-lin.cambridge.arm.com (e104803-lin.cambridge.arm.com [10.1.206.130]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id EB9D13F5B3; Fri, 20 Jul 2018 08:39:57 -0700 (PDT) From: Andre Przywara To: Andrew Jones Date: Fri, 20 Jul 2018 16:39:42 +0100 Message-Id: <20180720153942.26821-5-andre.przywara@arm.com> X-Mailer: git-send-email 2.14.4 In-Reply-To: <20180720153942.26821-1-andre.przywara@arm.com> References: <20180720153942.26821-1-andre.przywara@arm.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 217.140.101.70 Subject: [Qemu-devel] [kvm-unit-tests PATCH v2 4/4] arm/arm64: GICv2: add GICD_ITARGETSR testing X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , kvm@vger.kernel.org, Marc Zyngier , Christoffer Dall , qemu-devel@nongnu.org, Eric Auger , kvmarm@lists.cs.columbia.edu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Some tests for the ITARGETS registers. Bits corresponding to non-existent CPUs must be RAZ/WI. These registers must be byte-accessible, also check that accesses beyond the implemented IRQ limit are actually read-as-zero/write-ignore. Signed-off-by: Andre Przywara Reviewed-by: Andrew Jones --- arm/gic.c | 43 +++++++++++++++++++++++++++++++++++++++++++ lib/arm/asm/gic.h | 1 + 2 files changed, 44 insertions(+) diff --git a/arm/gic.c b/arm/gic.c index 57a2995..ed5642e 100644 --- a/arm/gic.c +++ b/arm/gic.c @@ -431,6 +431,46 @@ static void test_priorities(int nr_irqs, void *priptr) writel(orig_prio, first_spi); } =20 +/* GICD_ITARGETSR is only used by GICv2. */ +static void test_targets(int nr_irqs) +{ + void *targetsptr =3D gicv2_dist_base() + GICD_ITARGETSR; + u32 orig_targets; + u32 cpu_mask; + u32 pattern, reg; + + orig_targets =3D readl(targetsptr + GIC_FIRST_SPI); + report_prefix_push("ITARGETSR"); + + cpu_mask =3D (1 << nr_cpus) - 1; + cpu_mask |=3D cpu_mask << 8; + cpu_mask |=3D cpu_mask << 16; + + /* Check that bits for non implemented CPUs are RAZ/WI. */ + if (nr_cpus < 8) { + writel(0xffffffff, targetsptr + GIC_FIRST_SPI); + report("bits for %d non-existent CPUs masked", + !(readl(targetsptr + GIC_FIRST_SPI) & ~cpu_mask), + 8 - nr_cpus); + } else { + report_skip("CPU masking (all CPUs implemented)"); + } + + report("accesses beyond limit RAZ/WI", + test_readonly_32(targetsptr + nr_irqs, true)); + + pattern =3D 0x0103020f; + writel(pattern, targetsptr + GIC_FIRST_SPI); + reg =3D readl(targetsptr + GIC_FIRST_SPI); + report("register content preserved (%08x =3D> %08x)", + reg =3D=3D (pattern & cpu_mask), pattern & cpu_mask, reg); + + /* The TARGETS registers are byte accessible. */ + test_byte_access(targetsptr + GIC_FIRST_SPI, pattern, cpu_mask); + + writel(orig_targets, targetsptr + GIC_FIRST_SPI); +} + static void gic_test_mmio(void) { u32 reg; @@ -467,6 +507,9 @@ static void gic_test_mmio(void) reg); =20 test_priorities(nr_irqs, gic_dist_base + GICD_IPRIORITYR); + + if (gic_version() =3D=3D 2) + test_targets(nr_irqs); } =20 int main(int argc, char **argv) diff --git a/lib/arm/asm/gic.h b/lib/arm/asm/gic.h index a469645..f6dfb90 100644 --- a/lib/arm/asm/gic.h +++ b/lib/arm/asm/gic.h @@ -20,6 +20,7 @@ #define GICD_ISACTIVER 0x0300 #define GICD_ICACTIVER 0x0380 #define GICD_IPRIORITYR 0x0400 +#define GICD_ITARGETSR 0x0800 #define GICD_SGIR 0x0f00 #define GICD_ICPIDR2 0x0fe8 =20 --=20 2.14.4