From nobody Fri May 3 23:45:19 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1532098925776204.524512879535; Fri, 20 Jul 2018 08:02:05 -0700 (PDT) Received: from localhost ([::1]:48528 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fgWuy-0004F0-Oy for importer@patchew.org; Fri, 20 Jul 2018 11:02:04 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48746) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fgWqB-0000Y2-6L for qemu-devel@nongnu.org; Fri, 20 Jul 2018 10:57:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fgWqA-00064d-7R for qemu-devel@nongnu.org; Fri, 20 Jul 2018 10:57:07 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:43636) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fgWq4-0005xz-8C; Fri, 20 Jul 2018 10:57:00 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fgWpt-0004zg-4R; Fri, 20 Jul 2018 15:56:49 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Fri, 20 Jul 2018 15:56:44 +0100 Message-Id: <20180720145647.8810-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180720145647.8810-1-peter.maydell@linaro.org> References: <20180720145647.8810-1-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH 1/4] target/arm: Improve exception-taken logging X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Improve the exception-taken logging by logging in v7m_exception_taken() the exception we're going to take and whether it is secure/nonsecure. This requires us to move logging at many callsites from after the call to before it, so that the logging appears in a sensible order. (This will make tail-chaining produce more useful logs; for the current callers of v7m_exception_taken() we know which exception we're going to take, so custom log messages at the callsite sufficed; for tail-chaining only v7m_exception_taken() knows the exception number that we're going to tail-chain to.) Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/arm/helper.c | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 6f5bb198c3b..3ec6114599b 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6840,6 +6840,8 @@ static void v7m_exception_taken(ARMCPU *cpu, uint32_t= lr, bool dotailchain, bool push_failed =3D false; =20 armv7m_nvic_get_pending_irq_info(env->nvic, &exc, &targets_secure); + qemu_log_mask(CPU_LOG_INT, "...taking pending %s exception %d\n", + targets_secure ? "secure" : "nonsecure", exc); =20 if (arm_feature(env, ARM_FEATURE_V8)) { if (arm_feature(env, ARM_FEATURE_M_SECURITY) && @@ -6913,12 +6915,15 @@ static void v7m_exception_taken(ARMCPU *cpu, uint32= _t lr, bool dotailchain, * we might now want to take a different exception which * targets a different security state, so try again from the top. */ + qemu_log_mask(CPU_LOG_INT, + "...derived exception on callee-saves register stack= ing"); v7m_exception_taken(cpu, lr, true, true); return; } =20 if (!arm_v7m_load_vector(cpu, exc, targets_secure, &addr)) { /* Vector load failed: derived exception */ + qemu_log_mask(CPU_LOG_INT, "...derived exception on vector table l= oad"); v7m_exception_taken(cpu, lr, true, true); return; } @@ -7129,9 +7134,9 @@ static void do_v7m_exception_exit(ARMCPU *cpu) if (sfault) { env->v7m.sfsr |=3D R_V7M_SFSR_INVER_MASK; armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SECURE, false); - v7m_exception_taken(cpu, excret, true, false); qemu_log_mask(CPU_LOG_INT, "...taking SecureFault on existing " "stackframe: failed EXC_RETURN.ES validity check\n"); + v7m_exception_taken(cpu, excret, true, false); return; } =20 @@ -7141,9 +7146,9 @@ static void do_v7m_exception_exit(ARMCPU *cpu) */ env->v7m.cfsr[env->v7m.secure] |=3D R_V7M_CFSR_INVPC_MASK; armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, env->v7m.sec= ure); - v7m_exception_taken(cpu, excret, true, false); qemu_log_mask(CPU_LOG_INT, "...taking UsageFault on existing " "stackframe: failed exception return integrity check= \n"); + v7m_exception_taken(cpu, excret, true, false); return; } =20 @@ -7198,10 +7203,10 @@ static void do_v7m_exception_exit(ARMCPU *cpu) /* Take a SecureFault on the current stack */ env->v7m.sfsr |=3D R_V7M_SFSR_INVIS_MASK; armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SECURE, fal= se); - v7m_exception_taken(cpu, excret, true, false); qemu_log_mask(CPU_LOG_INT, "...taking SecureFault on exist= ing " "stackframe: failed exception return integri= ty " "signature check\n"); + v7m_exception_taken(cpu, excret, true, false); return; } =20 @@ -7234,6 +7239,7 @@ static void do_v7m_exception_exit(ARMCPU *cpu) /* v7m_stack_read() pended a fault, so take it (as a tail * chained exception on the same stack frame) */ + qemu_log_mask(CPU_LOG_INT, "...derived exception on unstacking= \n"); v7m_exception_taken(cpu, excret, true, false); return; } @@ -7270,10 +7276,10 @@ static void do_v7m_exception_exit(ARMCPU *cpu) armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, env->v7m.secure); env->v7m.cfsr[env->v7m.secure] |=3D R_V7M_CFSR_INVPC_MASK; - v7m_exception_taken(cpu, excret, true, false); qemu_log_mask(CPU_LOG_INT, "...taking UsageFault on existi= ng " "stackframe: failed exception return integri= ty " "check\n"); + v7m_exception_taken(cpu, excret, true, false); return; } } @@ -7309,9 +7315,9 @@ static void do_v7m_exception_exit(ARMCPU *cpu) armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, false); env->v7m.cfsr[env->v7m.secure] |=3D R_V7M_CFSR_INVPC_MASK; ignore_stackfaults =3D v7m_push_stack(cpu); - v7m_exception_taken(cpu, excret, false, ignore_stackfaults); qemu_log_mask(CPU_LOG_INT, "...taking UsageFault on new stackframe= : " "failed exception return integrity check\n"); + v7m_exception_taken(cpu, excret, false, ignore_stackfaults); return; } =20 @@ -7727,7 +7733,6 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) =20 ignore_stackfaults =3D v7m_push_stack(cpu); v7m_exception_taken(cpu, lr, false, ignore_stackfaults); - qemu_log_mask(CPU_LOG_INT, "... as %d\n", env->v7m.exception); } =20 /* Function used to synchronize QEMU's AArch64 register set with AArch32 --=20 2.17.1 From nobody Fri May 3 23:45:19 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 153209876901730.02786179569887; Fri, 20 Jul 2018 07:59:29 -0700 (PDT) Received: from localhost ([::1]:48503 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fgWsI-0001gK-4y for importer@patchew.org; Fri, 20 Jul 2018 10:59:18 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48728) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fgWq9-0000Vq-5R for qemu-devel@nongnu.org; Fri, 20 Jul 2018 10:57:06 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fgWq8-00063s-1n for qemu-devel@nongnu.org; Fri, 20 Jul 2018 10:57:05 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:43636) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fgWq3-0005xz-7Z; Fri, 20 Jul 2018 10:56:59 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fgWpt-0004zx-Qo; Fri, 20 Jul 2018 15:56:49 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Fri, 20 Jul 2018 15:56:45 +0100 Message-Id: <20180720145647.8810-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180720145647.8810-1-peter.maydell@linaro.org> References: <20180720145647.8810-1-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH 2/4] target/arm: Initialize exc_secure correctly in do_v7m_exception_exit() X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" In do_v7m_exception_exit(), we use the exc_secure variable to track whether the exception we're returning from is secure or non-secure. Unfortunately the statement initializing this was accidentally inside an "if (env->v7m.exception !=3D ARMV7M_EXCP_NMI)" conditional, which meant that we were using the wrong value for NMI handlers. Move the initialization out to the right place. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/arm/helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 3ec6114599b..efcadfc7fa9 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7052,6 +7052,7 @@ static void do_v7m_exception_exit(ARMCPU *cpu) /* For all other purposes, treat ES as 0 (R_HXSR) */ excret &=3D ~R_V7M_EXCRET_ES_MASK; } + exc_secure =3D excret & R_V7M_EXCRET_ES_MASK; } =20 if (env->v7m.exception !=3D ARMV7M_EXCP_NMI) { @@ -7062,7 +7063,6 @@ static void do_v7m_exception_exit(ARMCPU *cpu) * which security state's faultmask to clear. (v8M ARM ARM R_KBNF.) */ if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { - exc_secure =3D excret & R_V7M_EXCRET_ES_MASK; if (armv7m_nvic_raw_execution_priority(env->nvic) >=3D 0) { env->v7m.faultmask[exc_secure] =3D 0; } --=20 2.17.1 From nobody Fri May 3 23:45:19 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1532098779007268.17942854240107; Fri, 20 Jul 2018 07:59:39 -0700 (PDT) Received: from localhost ([::1]:48506 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fgWsW-0001pf-64 for importer@patchew.org; Fri, 20 Jul 2018 10:59:32 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48702) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fgWq5-0000UI-S3 for qemu-devel@nongnu.org; Fri, 20 Jul 2018 10:57:03 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fgWq4-00062n-RW for qemu-devel@nongnu.org; Fri, 20 Jul 2018 10:57:01 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:43636) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fgWq2-0005xz-8P; Fri, 20 Jul 2018 10:56:58 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fgWpu-00050T-NO; Fri, 20 Jul 2018 15:56:50 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Fri, 20 Jul 2018 15:56:46 +0100 Message-Id: <20180720145647.8810-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180720145647.8810-1-peter.maydell@linaro.org> References: <20180720145647.8810-1-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH 3/4] target/arm: Restore M-profile CONTROL.SPSEL before any tailchaining X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" On exception return for M-profile, we must restore the CONTROL.SPSEL bit from the EXCRET value before we do any kind of tailchaining, including for the derived exceptions on integrity check failures. Otherwise we will give the guest an incorrect EXCRET.SPSEL value on exception entry for the tailchained exception. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper.c | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index efcadfc7fa9..ff947416c9d 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7131,6 +7131,16 @@ static void do_v7m_exception_exit(ARMCPU *cpu) } } =20 + /* + * Set CONTROL.SPSEL from excret.SPSEL. Since we're still in + * Handler mode (and will be until we write the new XPSR.Interrupt + * field) this does not switch around the current stack pointer. + * We must do this before we do any kind of tailchaining, including + * for the derived exceptions on integrity check failures, or we will + * give the guest an incorrect EXCRET.SPSEL value on exception entry. + */ + write_v7m_control_spsel_for_secstate(env, return_to_sp_process, exc_se= cure); + if (sfault) { env->v7m.sfsr |=3D R_V7M_SFSR_INVER_MASK; armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SECURE, false); @@ -7152,12 +7162,6 @@ static void do_v7m_exception_exit(ARMCPU *cpu) return; } =20 - /* Set CONTROL.SPSEL from excret.SPSEL. Since we're still in - * Handler mode (and will be until we write the new XPSR.Interrupt - * field) this does not switch around the current stack pointer. - */ - write_v7m_control_spsel_for_secstate(env, return_to_sp_process, exc_se= cure); - switch_v7m_security_state(env, return_to_secure); =20 { --=20 2.17.1 From nobody Fri May 3 23:45:19 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1532098946374405.5885590522894; Fri, 20 Jul 2018 08:02:26 -0700 (PDT) Received: from localhost ([::1]:48529 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fgWvJ-0004P6-Cl for importer@patchew.org; Fri, 20 Jul 2018 11:02:25 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48677) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fgWq4-0000TW-M8 for qemu-devel@nongnu.org; Fri, 20 Jul 2018 10:57:03 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fgWq3-00061O-Lk for qemu-devel@nongnu.org; Fri, 20 Jul 2018 10:57:00 -0400 Received: from orth.archaic.org.uk ([2001:8b0:1d0::2]:43636) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fgWq1-0005xz-8U; Fri, 20 Jul 2018 10:56:57 -0400 Received: from pm215 by orth.archaic.org.uk with local (Exim 4.89) (envelope-from ) id 1fgWpv-00050y-Dz; Fri, 20 Jul 2018 15:56:51 +0100 From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Date: Fri, 20 Jul 2018 15:56:47 +0100 Message-Id: <20180720145647.8810-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180720145647.8810-1-peter.maydell@linaro.org> References: <20180720145647.8810-1-peter.maydell@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2001:8b0:1d0::2 Subject: [Qemu-devel] [PATCH 4/4] target/arm: Implement tailchaining for M profile cores X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: patches@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Tailchaining is an optimization in handling of exception return for M-profile cores: if we are about to pop the exception stack for an exception return, but there is a pending exception which is higher priority than the priority we are returning to, then instead of unstacking and then immediately taking the exception and stacking registers again, we can chain to the pending exception without unstacking and stacking. For v6M and v7M it is IMPDEF whether tailchaining happens for pending exceptions; for v8M this is architecturally required. Implement it in QEMU for all M-profile cores, since in practice v6M and v7M hardware implementations generally do have it. (We were already doing tailchaining for derived exceptions which happened during exception return, like the validity checks and stack access failures; these have always been required to be tailchained for all versions of the architecture.) Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index ff947416c9d..c9e9f95051c 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7162,6 +7162,22 @@ static void do_v7m_exception_exit(ARMCPU *cpu) return; } =20 + /* + * Tailchaining: if there is currently a pending exception that + * is high enough priority to preempt execution at the level we're + * about to return to, then just directly take that exception now, + * avoiding an unstack-and-then-stack. Note that now we have + * deactivated the previous exception by calling armv7m_nvic_complete_= irq() + * our current execution priority is already the execution priority we= are + * returning to -- none of the state we would unstack or set based on + * the EXCRET value affects it. + */ + if (armv7m_nvic_can_take_pending_exception(env->nvic)) { + qemu_log_mask(CPU_LOG_INT, "...tailchaining to pending exception\n= "); + v7m_exception_taken(cpu, excret, true, false); + return; + } + switch_v7m_security_state(env, return_to_secure); =20 { --=20 2.17.1