From nobody Wed Nov 5 02:37:51 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1531754199336255.0065444892316; Mon, 16 Jul 2018 08:16:39 -0700 (PDT) Received: from localhost ([::1]:52335 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ff5Es-0006Iz-AD for importer@patchew.org; Mon, 16 Jul 2018 11:16:38 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53347) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ff5D7-0005Jk-Qb for qemu-devel@nongnu.org; Mon, 16 Jul 2018 11:14:50 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ff5D2-0000AM-TI for qemu-devel@nongnu.org; Mon, 16 Jul 2018 11:14:49 -0400 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:41352 helo=foss.arm.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ff5D2-000082-Lp for qemu-devel@nongnu.org; Mon, 16 Jul 2018 11:14:44 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 753D215AD; Mon, 16 Jul 2018 08:14:43 -0700 (PDT) Received: from e104803-lin.lan (unknown [10.1.207.46]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 201F23F5A0; Mon, 16 Jul 2018 08:14:41 -0700 (PDT) From: Andre Przywara To: Andrew Jones Date: Mon, 16 Jul 2018 16:14:37 +0100 Message-Id: <20180716151438.9877-2-andre.przywara@arm.com> X-Mailer: git-send-email 2.14.4 In-Reply-To: <20180716151438.9877-1-andre.przywara@arm.com> References: <20180716151438.9877-1-andre.przywara@arm.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 217.140.101.70 Subject: [Qemu-devel] [kvm-unit-tests PATCH 1/2] arm64: timer: add TVAL accessors X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marc Zyngier , qemu-devel@nongnu.org, Christoffer Dall , kvm@vger.kernel.org, kvmarm@lists.cs.columbia.edu Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The ARM arch timer features the CVAL register, which holds an absolute value that is compared against the counter value. But there is also the TVAL register, which is defined as (CVAL - counter), and can be used to program or read relative timeouts. Add accessors for the TVAL register, to be able to read and write them easily later. Signed-off-by: Andre Przywara Reviewed-by: Andrew Jones --- arm/timer.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arm/timer.c b/arm/timer.c index 5f3135f..1c9ef44 100644 --- a/arm/timer.c +++ b/arm/timer.c @@ -40,6 +40,16 @@ static void write_vtimer_cval(u64 val) write_sysreg(val, cntv_cval_el0); } =20 +static s32 read_vtimer_tval(void) +{ + return read_sysreg(cntv_tval_el0); +} + +static void write_vtimer_tval(s32 val) +{ + write_sysreg(val, cntv_tval_el0); +} + static u64 read_vtimer_ctl(void) { return read_sysreg(cntv_ctl_el0); @@ -65,6 +75,16 @@ static void write_ptimer_cval(u64 val) write_sysreg(val, cntp_cval_el0); } =20 +static s32 read_ptimer_tval(void) +{ + return read_sysreg(cntp_tval_el0); +} + +static void write_ptimer_tval(s32 val) +{ + write_sysreg(val, cntp_tval_el0); +} + static u64 read_ptimer_ctl(void) { return read_sysreg(cntp_ctl_el0); @@ -82,6 +102,8 @@ struct timer_info { u64 (*read_counter)(void); u64 (*read_cval)(void); void (*write_cval)(u64); + s32 (*read_tval)(void); + void (*write_tval)(s32); u64 (*read_ctl)(void); void (*write_ctl)(u64); }; @@ -91,6 +113,8 @@ static struct timer_info vtimer_info =3D { .read_counter =3D read_vtimer_counter, .read_cval =3D read_vtimer_cval, .write_cval =3D write_vtimer_cval, + .read_tval =3D read_vtimer_tval, + .write_tval =3D write_vtimer_tval, .read_ctl =3D read_vtimer_ctl, .write_ctl =3D write_vtimer_ctl, }; @@ -100,6 +124,8 @@ static struct timer_info ptimer_info =3D { .read_counter =3D read_ptimer_counter, .read_cval =3D read_ptimer_cval, .write_cval =3D write_ptimer_cval, + .read_tval =3D read_ptimer_tval, + .write_tval =3D write_ptimer_tval, .read_ctl =3D read_ptimer_ctl, .write_ctl =3D write_ptimer_ctl, }; --=20 2.14.4