From nobody Tue Nov 4 23:53:46 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1531588788040370.50138569178137; Sat, 14 Jul 2018 10:19:48 -0700 (PDT) Received: from localhost ([::1]:42068 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1feOCr-0007gT-IN for importer@patchew.org; Sat, 14 Jul 2018 13:19:41 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38348) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1feO9q-0005m7-JM for qemu-devel@nongnu.org; Sat, 14 Jul 2018 13:16:38 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1feO9o-0004YJ-Jx for qemu-devel@nongnu.org; Sat, 14 Jul 2018 13:16:34 -0400 Received: from greensocs.com ([193.104.36.180]:57253) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1feO9i-0004MP-OK; Sat, 14 Jul 2018 13:16:27 -0400 Received: from localhost (localhost [127.0.0.1]) by greensocs.com (Postfix) with ESMTP id 9BCD5C7FA2; Sat, 14 Jul 2018 19:16:18 +0200 (CEST) Received: from greensocs.com ([127.0.0.1]) by localhost (gs-01.greensocs.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id if4eSR_Bzi6J; Sat, 14 Jul 2018 19:16:17 +0200 (CEST) Received: by greensocs.com (Postfix, from userid 998) id 8D73DC7AE3; Sat, 14 Jul 2018 19:16:17 +0200 (CEST) Received: from localhost.localdomain (unknown [105.98.38.216]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: luc.michel@greensocs.com) by greensocs.com (Postfix) with ESMTPSA id D8D84C7ADD; Sat, 14 Jul 2018 19:16:16 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1531588578; bh=m9WDuVhJ8xqlUr5PbtNbOeZfVH9fE/HRNe6eO4F6f3g=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=wt4RSS8lT65ZpoUKFBkpvCnbBNOEzJn7CHz7zkfC2GykoQqucFefIZNfYBiHy3sM/ 65Ry5TDxCAHdy2hgcHLgVOqzlM8rPAv6ZSvn2NdWpx0UYcNExYC0hhGHnbjRqETuZq 3hoWaQ/2UgSaGWxy7WlIzmcdYEb6pjb3gZk9r/Z0= X-Virus-Scanned: amavisd-new at greensocs.com Authentication-Results: gs-01.greensocs.com (amavisd-new); dkim=pass (1024-bit key) header.d=greensocs.com header.b=5d+5xGjZ; dkim=pass (1024-bit key) header.d=greensocs.com header.b=5d+5xGjZ DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1531588577; bh=m9WDuVhJ8xqlUr5PbtNbOeZfVH9fE/HRNe6eO4F6f3g=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=5d+5xGjZdsTlOMqUiP3BH5ar3nJ0WbcBY3fprTvrciwTtf6asLAyd9mLIBOwjGQQU ieGqvcaxsUbPHVLnkGFusFP0xd0RcYEkmGjbTD3NNxDBXWijI8/rl8XY3OEtOokoms MJL7aJI1pzi74LvKI/4CBkVwCE7zlMeIIlVvQfYo= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1531588577; bh=m9WDuVhJ8xqlUr5PbtNbOeZfVH9fE/HRNe6eO4F6f3g=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=5d+5xGjZdsTlOMqUiP3BH5ar3nJ0WbcBY3fprTvrciwTtf6asLAyd9mLIBOwjGQQU ieGqvcaxsUbPHVLnkGFusFP0xd0RcYEkmGjbTD3NNxDBXWijI8/rl8XY3OEtOokoms MJL7aJI1pzi74LvKI/4CBkVwCE7zlMeIIlVvQfYo= From: Luc Michel To: qemu-devel@nongnu.org Date: Sat, 14 Jul 2018 19:15:44 +0200 Message-Id: <20180714171601.5734-4-luc.michel@greensocs.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180714171601.5734-1-luc.michel@greensocs.com> References: <20180714171601.5734-1-luc.michel@greensocs.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 193.104.36.180 Subject: [Qemu-devel] [PATCH v4 03/20] intc/arm_gic: Remove some dead code and put some functions static X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , mark.burton@greensocs.com, saipava@xilinx.com, edgari@xilinx.com, qemu-arm@nongnu.org, Jan Kiszka , Luc Michel Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (found 2 invalid signatures) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" Some functions are now only used in arm_gic.c, put them static. Some of them where only used by the NVIC implementation and are not used anymore, so remove them. Signed-off-by: Luc Michel Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Peter Maydell --- hw/intc/arm_gic.c | 23 ++--------------------- hw/intc/gic_internal.h | 4 ---- 2 files changed, 2 insertions(+), 25 deletions(-) diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index accc03523b..9fe70e5519 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -71,7 +71,7 @@ static inline bool gic_has_groups(GICState *s) =20 /* TODO: Many places that call this routine could be optimized. */ /* Update interrupt status after enabled or pending bits have been changed= . */ -void gic_update(GICState *s) +static void gic_update(GICState *s) { int best_irq; int best_prio; @@ -137,19 +137,6 @@ void gic_update(GICState *s) } } =20 -void gic_set_pending_private(GICState *s, int cpu, int irq) -{ - int cm =3D 1 << cpu; - - if (gic_test_pending(s, irq, cm)) { - return; - } - - DPRINTF("Set %d pending cpu %d\n", irq, cpu); - GIC_DIST_SET_PENDING(irq, cm); - gic_update(s); -} - static void gic_set_irq_11mpcore(GICState *s, int irq, int level, int cm, int target) { @@ -565,7 +552,7 @@ static void gic_deactivate_irq(GICState *s, int cpu, in= t irq, MemTxAttrs attrs) GIC_DIST_CLEAR_ACTIVE(irq, cm); } =20 -void gic_complete_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs) +static void gic_complete_irq(GICState *s, int cpu, int irq, MemTxAttrs att= rs) { int cm =3D 1 << cpu; int group; @@ -1472,12 +1459,6 @@ static const MemoryRegionOps gic_cpu_ops =3D { .endianness =3D DEVICE_NATIVE_ENDIAN, }; =20 -/* This function is used by nvic model */ -void gic_init_irqs_and_distributor(GICState *s) -{ - gic_init_irqs_and_mmio(s, gic_set_irq, gic_ops); -} - static void arm_gic_realize(DeviceState *dev, Error **errp) { /* Device instance realize function for the GIC sysbus device */ diff --git a/hw/intc/gic_internal.h b/hw/intc/gic_internal.h index 6f8d242904..a2075a94db 100644 --- a/hw/intc/gic_internal.h +++ b/hw/intc/gic_internal.h @@ -75,11 +75,7 @@ /* The special cases for the revision property: */ #define REV_11MPCORE 0 =20 -void gic_set_pending_private(GICState *s, int cpu, int irq); uint32_t gic_acknowledge_irq(GICState *s, int cpu, MemTxAttrs attrs); -void gic_complete_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs); -void gic_update(GICState *s); -void gic_init_irqs_and_distributor(GICState *s); void gic_dist_set_priority(GICState *s, int cpu, int irq, uint8_t val, MemTxAttrs attrs); =20 --=20 2.18.0