From nobody Mon Feb 9 23:40:05 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1531588788212924.2834856963548; Sat, 14 Jul 2018 10:19:48 -0700 (PDT) Received: from localhost ([::1]:42066 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1feOCo-0007ea-Ff for importer@patchew.org; Sat, 14 Jul 2018 13:19:38 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38362) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1feO9q-0005mX-SH for qemu-devel@nongnu.org; Sat, 14 Jul 2018 13:16:38 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1feO9o-0004Xz-G0 for qemu-devel@nongnu.org; Sat, 14 Jul 2018 13:16:34 -0400 Received: from greensocs.com ([193.104.36.180]:57255) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1feO9i-0004MM-Mv; Sat, 14 Jul 2018 13:16:26 -0400 Received: from localhost (localhost [127.0.0.1]) by greensocs.com (Postfix) with ESMTP id BFF3FC7AFE; Sat, 14 Jul 2018 19:16:17 +0200 (CEST) Received: from greensocs.com ([127.0.0.1]) by localhost (gs-01.greensocs.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id epXyKaisCYkb; Sat, 14 Jul 2018 19:16:17 +0200 (CEST) Received: by greensocs.com (Postfix, from userid 998) id E6A6FC7AF9; Sat, 14 Jul 2018 19:16:16 +0200 (CEST) Received: from localhost.localdomain (unknown [105.98.38.216]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: luc.michel@greensocs.com) by greensocs.com (Postfix) with ESMTPSA id 1D45CC7AE3; Sat, 14 Jul 2018 19:16:16 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1531588577; bh=cH6+vpEmFdzTYRqDq6gwPorocs7nHSz3mVlAilMImI0=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=AsV+XrcVNCdUjvRjaYlH4YJOlI36CrVrag5RXYp3afKjLWbTTmKQ8LVwaqH/efaPc HbEHEFF28DKNf22QcSokgleOdS/0Go2y3HhLj90JtU87GkKxkW3fCCdEiMY1jpsSaa vu+cGCD/YpGcxKKnivftGuvC8LeKYfagTEHj6Lrg= X-Virus-Scanned: amavisd-new at greensocs.com Authentication-Results: gs-01.greensocs.com (amavisd-new); dkim=pass (1024-bit key) header.d=greensocs.com header.b=QuDcugKU; dkim=pass (1024-bit key) header.d=greensocs.com header.b=QuDcugKU DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1531588576; bh=cH6+vpEmFdzTYRqDq6gwPorocs7nHSz3mVlAilMImI0=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=QuDcugKUnlIDXEijgzSjngjzLC9DDBISgY9jG2OII/1w0fQ3J+bHbfKt+44GHGByr oSxqCgWL0UQ7Con+CzSZHFb2jjgtikiYowq7ONScu8puXzSVCy1HtLgZ8uwT2hASrP GvRGYNUO2rvOgK0Uxon1w+IyUa6hFN/08F+f5CL0= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1531588576; bh=cH6+vpEmFdzTYRqDq6gwPorocs7nHSz3mVlAilMImI0=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=QuDcugKUnlIDXEijgzSjngjzLC9DDBISgY9jG2OII/1w0fQ3J+bHbfKt+44GHGByr oSxqCgWL0UQ7Con+CzSZHFb2jjgtikiYowq7ONScu8puXzSVCy1HtLgZ8uwT2hASrP GvRGYNUO2rvOgK0Uxon1w+IyUa6hFN/08F+f5CL0= From: Luc Michel To: qemu-devel@nongnu.org Date: Sat, 14 Jul 2018 19:15:43 +0200 Message-Id: <20180714171601.5734-3-luc.michel@greensocs.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180714171601.5734-1-luc.michel@greensocs.com> References: <20180714171601.5734-1-luc.michel@greensocs.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 193.104.36.180 Subject: [Qemu-devel] [PATCH v4 02/20] intc/arm_gic: Implement GICD_ISACTIVERn and GICD_ICACTIVERn registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , mark.burton@greensocs.com, saipava@xilinx.com, edgari@xilinx.com, qemu-arm@nongnu.org, Jan Kiszka , Luc Michel Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (found 2 invalid signatures) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Implement GICD_ISACTIVERn and GICD_ICACTIVERn registers in the GICv2. Those registers allow to set or clear the active state of an IRQ in the distributor. Signed-off-by: Luc Michel Reviewed-by: Peter Maydell --- hw/intc/arm_gic.c | 61 +++++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 57 insertions(+), 4 deletions(-) diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index 6f3074ba88..accc03523b 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -711,8 +711,16 @@ static uint32_t gic_dist_readb(void *opaque, hwaddr of= fset, MemTxAttrs attrs) } } } else if (offset < 0x400) { - /* Interrupt Active. */ - irq =3D (offset - 0x300) * 8 + GIC_BASE_IRQ; + /* Interrupt Set/Clear Active. */ + if (offset < 0x380) { + irq =3D (offset - 0x300) * 8; + } else if (s->revision =3D=3D 2) { + irq =3D (offset - 0x380) * 8; + } else { + goto bad_reg; + } + + irq +=3D GIC_BASE_IRQ; if (irq >=3D s->num_irq) goto bad_reg; res =3D 0; @@ -991,9 +999,54 @@ static void gic_dist_writeb(void *opaque, hwaddr offse= t, GIC_DIST_CLEAR_PENDING(irq + i, ALL_CPU_MASK); } } + } else if (offset < 0x380) { + /* Interrupt Set Active. */ + if (s->revision !=3D 2) { + goto bad_reg; + } + + irq =3D (offset - 0x300) * 8 + GIC_BASE_IRQ; + if (irq >=3D s->num_irq) { + goto bad_reg; + } + + /* This register is banked per-cpu for PPIs */ + int cm =3D irq < GIC_INTERNAL ? (1 << cpu) : ALL_CPU_MASK; + + for (i =3D 0; i < 8; i++) { + if (s->security_extn && !attrs.secure && + !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) { + continue; /* Ignore Non-secure access of Group0 IRQ */ + } + + if (value & (1 << i)) { + GIC_DIST_SET_ACTIVE(irq + i, cm); + } + } } else if (offset < 0x400) { - /* Interrupt Active. */ - goto bad_reg; + /* Interrupt Clear Active. */ + if (s->revision !=3D 2) { + goto bad_reg; + } + + irq =3D (offset - 0x380) * 8 + GIC_BASE_IRQ; + if (irq >=3D s->num_irq) { + goto bad_reg; + } + + /* This register is banked per-cpu for PPIs */ + int cm =3D irq < GIC_INTERNAL ? (1 << cpu) : ALL_CPU_MASK; + + for (i =3D 0; i < 8; i++) { + if (s->security_extn && !attrs.secure && + !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) { + continue; /* Ignore Non-secure access of Group0 IRQ */ + } + + if (value & (1 << i)) { + GIC_DIST_CLEAR_ACTIVE(irq + i, cm); + } + } } else if (offset < 0x800) { /* Interrupt Priority. */ irq =3D (offset - 0x400) + GIC_BASE_IRQ; --=20 2.18.0