From nobody Tue Nov 4 23:55:36 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1531589147066409.5344892913532; Sat, 14 Jul 2018 10:25:47 -0700 (PDT) Received: from localhost ([::1]:42109 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1feOIb-0004MA-7x for importer@patchew.org; Sat, 14 Jul 2018 13:25:37 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38572) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1feO9y-0005tN-H6 for qemu-devel@nongnu.org; Sat, 14 Jul 2018 13:16:43 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1feO9w-0004in-QY for qemu-devel@nongnu.org; Sat, 14 Jul 2018 13:16:42 -0400 Received: from greensocs.com ([193.104.36.180]:57388) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1feO9p-0004Zk-Kn; Sat, 14 Jul 2018 13:16:33 -0400 Received: from localhost (localhost [127.0.0.1]) by greensocs.com (Postfix) with ESMTP id 13792C7ADD; Sat, 14 Jul 2018 19:16:33 +0200 (CEST) Received: from greensocs.com ([127.0.0.1]) by localhost (gs-01.greensocs.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 5W9HTGdt_srp; Sat, 14 Jul 2018 19:16:32 +0200 (CEST) Received: by greensocs.com (Postfix, from userid 998) id 3332AC7AF4; Sat, 14 Jul 2018 19:16:31 +0200 (CEST) Received: from localhost.localdomain (unknown [105.98.38.216]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: luc.michel@greensocs.com) by greensocs.com (Postfix) with ESMTPSA id 3BBA8C7AE3; Sat, 14 Jul 2018 19:16:30 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1531588593; bh=i1BwjH3XT+OrsK2Nj8m0xiz7tDcSdqowdxOMe+UKIks=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=bYpaGqZoxJhsn6zziZvPggjOPVoUEKtRFbrI1QoUA0SsF9R96DdL2sM60rJbqlHvj DCgbSm6/Puuhj9Gr18AYkkj/DJZPokntGfnF9vLS9pgJy2SIhS9AJN/hdhFOQ2m0j1 UtIniTwLzDwyqPBN4zP3y5qikVQlqGlaIUiKvUbY= X-Virus-Scanned: amavisd-new at greensocs.com Authentication-Results: gs-01.greensocs.com (amavisd-new); dkim=pass (1024-bit key) header.d=greensocs.com header.b=qbXMgKJ9; dkim=pass (1024-bit key) header.d=greensocs.com header.b=qbXMgKJ9 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1531588591; bh=i1BwjH3XT+OrsK2Nj8m0xiz7tDcSdqowdxOMe+UKIks=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=qbXMgKJ9ODnQklMe7JiwxtM8ic6iZ04Zpd1d/PEOISyzDpuohcUixgBEkZVva/gf6 yR9MkF9yzq0QkCS7YUd0yCVCX1iVqvxDRSVL2KNv/GtA7X3MsGKpnPdr+rcRaxa9p2 lMwuSb4gHxyiwIhDuTWcqkLJATq4bKaG3DYkDuiU= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1531588591; bh=i1BwjH3XT+OrsK2Nj8m0xiz7tDcSdqowdxOMe+UKIks=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=qbXMgKJ9ODnQklMe7JiwxtM8ic6iZ04Zpd1d/PEOISyzDpuohcUixgBEkZVva/gf6 yR9MkF9yzq0QkCS7YUd0yCVCX1iVqvxDRSVL2KNv/GtA7X3MsGKpnPdr+rcRaxa9p2 lMwuSb4gHxyiwIhDuTWcqkLJATq4bKaG3DYkDuiU= From: Luc Michel To: qemu-devel@nongnu.org Date: Sat, 14 Jul 2018 19:15:58 +0200 Message-Id: <20180714171601.5734-18-luc.michel@greensocs.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180714171601.5734-1-luc.michel@greensocs.com> References: <20180714171601.5734-1-luc.michel@greensocs.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 193.104.36.180 Subject: [Qemu-devel] [PATCH v4 17/20] intc/arm_gic: Implement maintenance interrupt generation X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , mark.burton@greensocs.com, saipava@xilinx.com, edgari@xilinx.com, qemu-arm@nongnu.org, Jan Kiszka , Luc Michel Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (found 2 invalid signatures) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Implement the maintenance interrupt generation that is part of the GICv2 virtualization extensions. Signed-off-by: Luc Michel Reviewed-by: Peter Maydell --- hw/intc/arm_gic.c | 97 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 97 insertions(+) diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index 85f1a03147..4155fbe667 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -240,9 +240,106 @@ static inline bool gic_lr_entry_is_eoi(uint32_t entry) && !GICH_LR_HW(entry) && GICH_LR_EOI(entry); } =20 +static inline void gic_extract_lr_info(GICState *s, int cpu, + int *num_eoi, int *num_valid, int *num_pen= ding) +{ + int lr_idx; + + *num_eoi =3D 0; + *num_valid =3D 0; + *num_pending =3D 0; + + for (lr_idx =3D 0; lr_idx < s->num_lrs; lr_idx++) { + uint32_t *entry =3D &s->h_lr[lr_idx][cpu]; + + if (gic_lr_entry_is_eoi(*entry)) { + (*num_eoi)++; + } + + if (GICH_LR_STATE(*entry) !=3D GICH_LR_STATE_INVALID) { + (*num_valid)++; + } + + if (GICH_LR_STATE(*entry) =3D=3D GICH_LR_STATE_PENDING) { + (*num_pending)++; + } + } +} + +static void gic_compute_misr(GICState *s, int cpu) +{ + uint32_t value =3D 0; + int vcpu =3D cpu + GIC_NCPU; + + int num_eoi, num_valid, num_pending; + + gic_extract_lr_info(s, cpu, &num_eoi, &num_valid, &num_pending); + + /* EOI */ + if (num_eoi) { + value |=3D R_GICH_MISR_EOI_MASK; + } + + /* U: true if only 0 or 1 LR entry is valid */ + if ((s->h_hcr[cpu] & R_GICH_HCR_UIE_MASK) && (num_valid < 2)) { + value |=3D R_GICH_MISR_U_MASK; + } + + /* LRENP: EOICount is not 0 */ + if ((s->h_hcr[cpu] & R_GICH_HCR_LRENPIE_MASK) && + ((s->h_hcr[cpu] & R_GICH_HCR_EOICount_MASK) !=3D 0)) { + value |=3D R_GICH_MISR_LRENP_MASK; + } + + /* NP: no pending interrupts */ + if ((s->h_hcr[cpu] & R_GICH_HCR_NPIE_MASK) && (num_pending =3D=3D 0)) { + value |=3D R_GICH_MISR_NP_MASK; + } + + /* VGrp0E: group0 virq signaling enabled */ + if ((s->h_hcr[cpu] & R_GICH_HCR_VGRP0EIE_MASK) && + (s->cpu_ctlr[vcpu] & GICC_CTLR_EN_GRP0)) { + value |=3D R_GICH_MISR_VGrp0E_MASK; + } + + /* VGrp0D: group0 virq signaling disabled */ + if ((s->h_hcr[cpu] & R_GICH_HCR_VGRP0DIE_MASK) && + !(s->cpu_ctlr[vcpu] & GICC_CTLR_EN_GRP0)) { + value |=3D R_GICH_MISR_VGrp0D_MASK; + } + + /* VGrp1E: group1 virq signaling enabled */ + if ((s->h_hcr[cpu] & R_GICH_HCR_VGRP1EIE_MASK) && + (s->cpu_ctlr[vcpu] & GICC_CTLR_EN_GRP1)) { + value |=3D R_GICH_MISR_VGrp1E_MASK; + } + + /* VGrp1D: group1 virq signaling disabled */ + if ((s->h_hcr[cpu] & R_GICH_HCR_VGRP1DIE_MASK) && + !(s->cpu_ctlr[vcpu] & GICC_CTLR_EN_GRP1)) { + value |=3D R_GICH_MISR_VGrp1D_MASK; + } + + s->h_misr[cpu] =3D value; +} + +static void gic_update_maintenance(GICState *s) +{ + int cpu =3D 0; + int maint_level; + + for (cpu =3D 0; cpu < s->num_cpu; cpu++) { + gic_compute_misr(s, cpu); + maint_level =3D (s->h_hcr[cpu] & R_GICH_HCR_EN_MASK) && s->h_misr[= cpu]; + + qemu_set_irq(s->maintenance_irq[cpu], maint_level); + } +} + static void gic_update_virt(GICState *s) { gic_update_internal(s, true); + gic_update_maintenance(s); } =20 static void gic_set_irq_11mpcore(GICState *s, int irq, int level, --=20 2.18.0