From nobody Tue Nov 4 23:55:36 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (208.118.235.17 [208.118.235.17]) by mx.zohomail.com with SMTPS id 1531589526157824.2181516933175; Sat, 14 Jul 2018 10:32:06 -0700 (PDT) Received: from localhost ([::1]:42151 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1feOOi-0000Xh-9B for importer@patchew.org; Sat, 14 Jul 2018 13:31:56 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38527) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1feO9w-0005qb-T8 for qemu-devel@nongnu.org; Sat, 14 Jul 2018 13:16:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1feO9u-0004fq-Mj for qemu-devel@nongnu.org; Sat, 14 Jul 2018 13:16:40 -0400 Received: from greensocs.com ([193.104.36.180]:57343) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1feO9l-0004UN-TA; Sat, 14 Jul 2018 13:16:30 -0400 Received: from localhost (localhost [127.0.0.1]) by greensocs.com (Postfix) with ESMTP id DB88FC7AF0; Sat, 14 Jul 2018 19:16:28 +0200 (CEST) Received: from greensocs.com ([127.0.0.1]) by localhost (gs-01.greensocs.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Zp0ytQcj14Oy; Sat, 14 Jul 2018 19:16:28 +0200 (CEST) Received: by greensocs.com (Postfix, from userid 998) id F2207C7ADD; Sat, 14 Jul 2018 19:16:27 +0200 (CEST) Received: from localhost.localdomain (unknown [105.98.38.216]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: luc.michel@greensocs.com) by greensocs.com (Postfix) with ESMTPSA id 40AC1C7AE3; Sat, 14 Jul 2018 19:16:27 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1531588588; bh=gz2wz+zEPSs+qe9FFQpxhPmAyov+ZYPoqU7uxXP/pZY=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=eFhN31X7kMGqPOCSeQ0SZaS7xuyBFpkvkXAl+EOoBdEqWFInWZ8ts8jt8eMT1P62C xfj+QYQvG8Xn9Cdkl3YtvE2dyF0oGR9K9FpUjMi9S5SJKHqBgp5Gy2UlQ71NVr8iB3 bcnMYVqVqYZ5mtNRoYhlPYpAVMq5XMy7A/KPBxcY= X-Virus-Scanned: amavisd-new at greensocs.com Authentication-Results: gs-01.greensocs.com (amavisd-new); dkim=pass (1024-bit key) header.d=greensocs.com header.b=Ekq/0qtI; dkim=pass (1024-bit key) header.d=greensocs.com header.b=Ekq/0qtI DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1531588587; bh=gz2wz+zEPSs+qe9FFQpxhPmAyov+ZYPoqU7uxXP/pZY=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=Ekq/0qtIJuUfWECkpf5GsCpjHCEo0rQuTJPzx10A+/OWHPpsUzM0u+Og/WXzOqm1v VCKSFFXfChlk46L0FfDJQeHwuySfie8zOIfLRitwaSx2nxhxG+TF6m511ZmhBnpzh0 sYNQs4CFDg6PoO+UG/V6+vy3Ic7qu4emH1VnzI2M= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1531588587; bh=gz2wz+zEPSs+qe9FFQpxhPmAyov+ZYPoqU7uxXP/pZY=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=Ekq/0qtIJuUfWECkpf5GsCpjHCEo0rQuTJPzx10A+/OWHPpsUzM0u+Og/WXzOqm1v VCKSFFXfChlk46L0FfDJQeHwuySfie8zOIfLRitwaSx2nxhxG+TF6m511ZmhBnpzh0 sYNQs4CFDg6PoO+UG/V6+vy3Ic7qu4emH1VnzI2M= From: Luc Michel To: qemu-devel@nongnu.org Date: Sat, 14 Jul 2018 19:15:55 +0200 Message-Id: <20180714171601.5734-15-luc.michel@greensocs.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180714171601.5734-1-luc.michel@greensocs.com> References: <20180714171601.5734-1-luc.michel@greensocs.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 193.104.36.180 Subject: [Qemu-devel] [PATCH v4 14/20] intc/arm_gic: Wire the vCPU interface X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , mark.burton@greensocs.com, saipava@xilinx.com, edgari@xilinx.com, qemu-arm@nongnu.org, Jan Kiszka , Luc Michel Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (found 2 invalid signatures) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add the read/write functions to handle accesses to the vCPU interface. Those accesses are forwarded to the real CPU interface, with the CPU id being converted to the corresponding vCPU id (vCPU id =3D CPU id + GIC_NCPU). As for the CPU interface, we create a base region for the vCPU interface that fetches the current vCPU id using the current_cpu global variable, and one mirror region per vCPU which maps to that specific vCPU id. This is required by the GIC architecture specification. Signed-off-by: Luc Michel --- hw/intc/arm_gic.c | 37 +++++++++++++++++++++++++++++++++++-- 1 file changed, 35 insertions(+), 2 deletions(-) diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index 28ecf0c1fc..be44015c39 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -1514,6 +1514,23 @@ static MemTxResult gic_do_cpu_write(void *opaque, hw= addr addr, return gic_cpu_write(s, id, addr, value, attrs); } =20 +static MemTxResult gic_thisvcpu_read(void *opaque, hwaddr addr, uint64_t *= data, + unsigned size, MemTxAttrs attrs) +{ + GICState *s =3D (GICState *)opaque; + + return gic_cpu_read(s, gic_get_current_vcpu(s), addr, data, attrs); +} + +static MemTxResult gic_thisvcpu_write(void *opaque, hwaddr addr, + uint64_t value, unsigned size, + MemTxAttrs attrs) +{ + GICState *s =3D (GICState *)opaque; + + return gic_cpu_write(s, gic_get_current_vcpu(s), addr, value, attrs); +} + static const MemoryRegionOps gic_ops[2] =3D { { .read_with_attrs =3D gic_dist_read, @@ -1533,6 +1550,19 @@ static const MemoryRegionOps gic_cpu_ops =3D { .endianness =3D DEVICE_NATIVE_ENDIAN, }; =20 +static const MemoryRegionOps gic_virt_ops[2] =3D { + { + .read_with_attrs =3D NULL, + .write_with_attrs =3D NULL, + .endianness =3D DEVICE_NATIVE_ENDIAN, + }, + { + .read_with_attrs =3D gic_thisvcpu_read, + .write_with_attrs =3D gic_thisvcpu_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, + } +}; + static void arm_gic_realize(DeviceState *dev, Error **errp) { /* Device instance realize function for the GIC sysbus device */ @@ -1554,8 +1584,11 @@ static void arm_gic_realize(DeviceState *dev, Error = **errp) return; } =20 - /* This creates distributor and main CPU interface (s->cpuiomem[0]) */ - gic_init_irqs_and_mmio(s, gic_set_irq, gic_ops, NULL); + /* This creates distributor, main CPU interface (s->cpuiomem[0]) and if + * enabled, virtualization extensions related interfaces (main virtual + * interface (s->vifaceiomem[0]) and virtual CPU interface). + */ + gic_init_irqs_and_mmio(s, gic_set_irq, gic_ops, gic_virt_ops); =20 /* Extra core-specific regions for the CPU interfaces. This is * necessary for "franken-GIC" implementations, for example on --=20 2.18.0