From nobody Tue Nov 4 23:55:36 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1531589297457771.949856617058; Sat, 14 Jul 2018 10:28:17 -0700 (PDT) Received: from localhost ([::1]:42132 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1feOLA-0006YD-FU for importer@patchew.org; Sat, 14 Jul 2018 13:28:16 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38479) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1feO9v-0005oc-8w for qemu-devel@nongnu.org; Sat, 14 Jul 2018 13:16:41 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1feO9r-0004cF-DK for qemu-devel@nongnu.org; Sat, 14 Jul 2018 13:16:39 -0400 Received: from greensocs.com ([193.104.36.180]:57331) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1feO9k-0004Sm-HL; Sat, 14 Jul 2018 13:16:28 -0400 Received: from localhost (localhost [127.0.0.1]) by greensocs.com (Postfix) with ESMTP id 0721FC7AF9; Sat, 14 Jul 2018 19:16:28 +0200 (CEST) Received: from greensocs.com ([127.0.0.1]) by localhost (gs-01.greensocs.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id MSDtLllt23UU; Sat, 14 Jul 2018 19:16:27 +0200 (CEST) Received: by greensocs.com (Postfix, from userid 998) id 2E387C7AFC; Sat, 14 Jul 2018 19:16:27 +0200 (CEST) Received: from localhost.localdomain (unknown [105.98.38.216]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: luc.michel@greensocs.com) by greensocs.com (Postfix) with ESMTPSA id 792D742898C; Sat, 14 Jul 2018 19:16:26 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1531588588; bh=Bt7CiwOXI1Ge9roLoaK10EKjQ2cv9jRbjFAHV2MrjRI=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=2qlVVwAhxec1YMoZ8AY8BiSVyyBhMFbIGph1dYKDX88JgvhLzXvHCZMctKZPXwF/q Njnnqzulr0Nc94n6guEhk2rSRWwCCAQxawANcrjgUYHDqYClWLYtf6HKwFLZJ4Ou6j mAayRiJ446zNvmEC8LEnQZ0TQBxNMNcSHYs5u3Es= X-Virus-Scanned: amavisd-new at greensocs.com Authentication-Results: gs-01.greensocs.com (amavisd-new); dkim=pass (1024-bit key) header.d=greensocs.com header.b=KOuNkQ6x; dkim=pass (1024-bit key) header.d=greensocs.com header.b=KOuNkQ6x DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1531588587; bh=Bt7CiwOXI1Ge9roLoaK10EKjQ2cv9jRbjFAHV2MrjRI=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=KOuNkQ6xpwoImryLzbrhWjFIB3Q5Ushb1y6T4B1S0hX8Vbtb+k3wr8+NFdNVzbcPv 75uxJ8/4t3VS0buHEScWBSMY41X6e8f4zQL95fLdK0cXNQBqIbPsJ86GiWD9RvIb7M xdcwQUZtbaI/ce435HX/KwGU2LY/EbP9p1smVzHY= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1531588587; bh=Bt7CiwOXI1Ge9roLoaK10EKjQ2cv9jRbjFAHV2MrjRI=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=KOuNkQ6xpwoImryLzbrhWjFIB3Q5Ushb1y6T4B1S0hX8Vbtb+k3wr8+NFdNVzbcPv 75uxJ8/4t3VS0buHEScWBSMY41X6e8f4zQL95fLdK0cXNQBqIbPsJ86GiWD9RvIb7M xdcwQUZtbaI/ce435HX/KwGU2LY/EbP9p1smVzHY= From: Luc Michel To: qemu-devel@nongnu.org Date: Sat, 14 Jul 2018 19:15:54 +0200 Message-Id: <20180714171601.5734-14-luc.michel@greensocs.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180714171601.5734-1-luc.michel@greensocs.com> References: <20180714171601.5734-1-luc.michel@greensocs.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 193.104.36.180 Subject: [Qemu-devel] [PATCH v4 13/20] intc/arm_gic: Implement virtualization extensions in gic_cpu_(read|write) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , mark.burton@greensocs.com, saipava@xilinx.com, edgari@xilinx.com, qemu-arm@nongnu.org, Jan Kiszka , Luc Michel Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (found 2 invalid signatures) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Implement virtualization extensions in the gic_cpu_read() and gic_cpu_write() functions. Those are the last bits missing to fully support virtualization extensions in the CPU interface path. Signed-off-by: Luc Michel Reviewed-by: Peter Maydell --- hw/intc/arm_gic.c | 20 +++++++++++++++----- 1 file changed, 15 insertions(+), 5 deletions(-) diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index 50cbbfbe24..28ecf0c1fc 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -1360,9 +1360,12 @@ static MemTxResult gic_cpu_read(GICState *s, int cpu= , int offset, case 0xd0: case 0xd4: case 0xd8: case 0xdc: { int regno =3D (offset - 0xd0) / 4; + int nr_aprs =3D gic_is_vcpu(cpu) ? GIC_VIRT_NR_APRS : GIC_NR_APRS; =20 - if (regno >=3D GIC_NR_APRS || s->revision !=3D 2) { + if (regno >=3D nr_aprs || s->revision !=3D 2) { *data =3D 0; + } else if (gic_is_vcpu(cpu)) { + *data =3D s->h_apr[gic_get_vcpu_real_id(cpu)]; } else if (gic_cpu_ns_access(s, cpu, attrs)) { /* NS view of GICC_APR is the top half of GIC_NSAPR */ *data =3D gic_apr_ns_view(s, regno, cpu); @@ -1376,7 +1379,7 @@ static MemTxResult gic_cpu_read(GICState *s, int cpu,= int offset, int regno =3D (offset - 0xe0) / 4; =20 if (regno >=3D GIC_NR_APRS || s->revision !=3D 2 || !gic_has_group= s(s) || - gic_cpu_ns_access(s, cpu, attrs)) { + gic_cpu_ns_access(s, cpu, attrs) || gic_is_vcpu(cpu)) { *data =3D 0; } else { *data =3D s->nsapr[regno][cpu]; @@ -1411,7 +1414,8 @@ static MemTxResult gic_cpu_write(GICState *s, int cpu= , int offset, s->abpr[cpu] =3D MAX(value & 0x7, GIC_MIN_ABPR); } } else { - s->bpr[cpu] =3D MAX(value & 0x7, GIC_MIN_BPR); + int min_bpr =3D gic_is_vcpu(cpu) ? GIC_VIRT_MIN_BPR : GIC_MIN_= BPR; + s->bpr[cpu] =3D MAX(value & 0x7, min_bpr); } break; case 0x10: /* End Of Interrupt */ @@ -1428,11 +1432,14 @@ static MemTxResult gic_cpu_write(GICState *s, int c= pu, int offset, case 0xd0: case 0xd4: case 0xd8: case 0xdc: { int regno =3D (offset - 0xd0) / 4; + int nr_aprs =3D gic_is_vcpu(cpu) ? GIC_VIRT_NR_APRS : GIC_NR_APRS; =20 - if (regno >=3D GIC_NR_APRS || s->revision !=3D 2) { + if (regno >=3D nr_aprs || s->revision !=3D 2) { return MEMTX_OK; } - if (gic_cpu_ns_access(s, cpu, attrs)) { + if (gic_is_vcpu(cpu)) { + s->h_apr[gic_get_vcpu_real_id(cpu)] =3D value; + } else if (gic_cpu_ns_access(s, cpu, attrs)) { /* NS view of GICC_APR is the top half of GIC_NSAPR */ gic_apr_write_ns_view(s, regno, cpu, value); } else { @@ -1447,6 +1454,9 @@ static MemTxResult gic_cpu_write(GICState *s, int cpu= , int offset, if (regno >=3D GIC_NR_APRS || s->revision !=3D 2) { return MEMTX_OK; } + if (gic_is_vcpu(cpu)) { + return MEMTX_OK; + } if (!gic_has_groups(s) || (gic_cpu_ns_access(s, cpu, attrs))) { return MEMTX_OK; } --=20 2.18.0