From nobody Tue Nov 4 23:55:37 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 1531588977571992.0288505661389; Sat, 14 Jul 2018 10:22:57 -0700 (PDT) Received: from localhost ([::1]:42089 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1feOG0-0001pN-Ce for importer@patchew.org; Sat, 14 Jul 2018 13:22:56 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38376) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1feO9r-0005mr-8s for qemu-devel@nongnu.org; Sat, 14 Jul 2018 13:16:39 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1feO9p-0004ZP-8v for qemu-devel@nongnu.org; Sat, 14 Jul 2018 13:16:35 -0400 Received: from greensocs.com ([193.104.36.180]:57316) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1feO9j-0004QU-FT; Sat, 14 Jul 2018 13:16:27 -0400 Received: from localhost (localhost [127.0.0.1]) by greensocs.com (Postfix) with ESMTP id A6DBE443480; Sat, 14 Jul 2018 19:16:25 +0200 (CEST) Received: from greensocs.com ([127.0.0.1]) by localhost (gs-01.greensocs.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id hopGqZN0Y-EY; Sat, 14 Jul 2018 19:16:24 +0200 (CEST) Received: by greensocs.com (Postfix, from userid 998) id C364DC7AF0; Sat, 14 Jul 2018 19:16:24 +0200 (CEST) Received: from localhost.localdomain (unknown [105.98.38.216]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: luc.michel@greensocs.com) by greensocs.com (Postfix) with ESMTPSA id 18B10C7ADD; Sat, 14 Jul 2018 19:16:24 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1531588585; bh=gAGn4PasunLM8q8SMWKDBFXch2i23lCbZ04LlKRrBME=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=fUmqbDx3JsU1zuPFZd8sIqkF0qTFeP1CHDgRQcHN/7SnQy+kUg7uxYfhXVz+qiRqi PT88mjEa/m0nWmdKAmaxas5LuaL48XEg2uEv0uQ1BkQkfDGRfuiaoxXZPtjr0zvRxO fnJ6XGw09hX90zkM0Z7/rwobU1iiMxbp86SFHGoQ= X-Virus-Scanned: amavisd-new at greensocs.com Authentication-Results: gs-01.greensocs.com (amavisd-new); dkim=pass (1024-bit key) header.d=greensocs.com header.b=bjz9MlO1; dkim=pass (1024-bit key) header.d=greensocs.com header.b=bjz9MlO1 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1531588584; bh=gAGn4PasunLM8q8SMWKDBFXch2i23lCbZ04LlKRrBME=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=bjz9MlO1anu/gWPjkJ+z2Sp21s0QTe7EvHq+rclzryNftJv8JP8FL/teSGctHgxSG UPPMVZ7HgtdcLBnUIUADNSXeSovh0TxEnJu9RF+aLtOIv2M80iThRXRhwhEAolILO2 88YkerfI4Cw8qoI+YJwRjsMzd42QDLKBv1JX5z7U= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=greensocs.com; s=mail; t=1531588584; bh=gAGn4PasunLM8q8SMWKDBFXch2i23lCbZ04LlKRrBME=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=bjz9MlO1anu/gWPjkJ+z2Sp21s0QTe7EvHq+rclzryNftJv8JP8FL/teSGctHgxSG UPPMVZ7HgtdcLBnUIUADNSXeSovh0TxEnJu9RF+aLtOIv2M80iThRXRhwhEAolILO2 88YkerfI4Cw8qoI+YJwRjsMzd42QDLKBv1JX5z7U= From: Luc Michel To: qemu-devel@nongnu.org Date: Sat, 14 Jul 2018 19:15:51 +0200 Message-Id: <20180714171601.5734-11-luc.michel@greensocs.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180714171601.5734-1-luc.michel@greensocs.com> References: <20180714171601.5734-1-luc.michel@greensocs.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 193.104.36.180 Subject: [Qemu-devel] [PATCH v4 10/20] intc/arm_gic: Implement virtualization extensions in gic_(activate_irq|drop_prio) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , mark.burton@greensocs.com, saipava@xilinx.com, edgari@xilinx.com, qemu-arm@nongnu.org, Jan Kiszka , Luc Michel Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (found 2 invalid signatures) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Implement virtualization extensions in gic_activate_irq() and gic_drop_prio() and in gic_get_prio_from_apr_bits() called by gic_drop_prio(). When the current CPU is a vCPU: - Use GIC_VIRT_MIN_BPR and GIC_VIRT_NR_APRS instead of their non-virt counterparts, - the vCPU APR is stored in the virtual interface, in h_apr. Signed-off-by: Luc Michel Reviewed-by: Peter Maydell --- hw/intc/arm_gic.c | 50 +++++++++++++++++++++++++++++++++++------------ 1 file changed, 38 insertions(+), 12 deletions(-) diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index ad241d12c2..60704cabbb 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -276,16 +276,23 @@ static void gic_activate_irq(GICState *s, int cpu, in= t irq) * and update the running priority. */ int prio =3D gic_get_group_priority(s, cpu, irq); - int preemption_level =3D prio >> (GIC_MIN_BPR + 1); + int min_bpr =3D gic_is_vcpu(cpu) ? GIC_VIRT_MIN_BPR : GIC_MIN_BPR; + int preemption_level =3D prio >> (min_bpr + 1); int regno =3D preemption_level / 32; int bitno =3D preemption_level % 32; + uint32_t *papr =3D NULL; =20 - if (gic_has_groups(s) && gic_test_group(s, irq, cpu)) { - s->nsapr[regno][cpu] |=3D (1 << bitno); + if (gic_is_vcpu(cpu)) { + assert(regno =3D=3D 0); + papr =3D &s->h_apr[gic_get_vcpu_real_id(cpu)]; + } else if (gic_has_groups(s) && gic_test_group(s, irq, cpu)) { + papr =3D &s->nsapr[regno][cpu]; } else { - s->apr[regno][cpu] |=3D (1 << bitno); + papr =3D &s->apr[regno][cpu]; } =20 + *papr |=3D (1 << bitno); + s->running_priority[cpu] =3D prio; gic_set_active(s, irq, cpu); } @@ -296,6 +303,16 @@ static int gic_get_prio_from_apr_bits(GICState *s, int= cpu) * on the set bits in the Active Priority Registers. */ int i; + + if (gic_is_vcpu(cpu)) { + uint32_t apr =3D s->h_apr[gic_get_vcpu_real_id(cpu)]; + if (apr) { + return ctz32(apr) << (GIC_VIRT_MIN_BPR + 1); + } else { + return 0x100; + } + } + for (i =3D 0; i < GIC_NR_APRS; i++) { uint32_t apr =3D s->apr[i][cpu] | s->nsapr[i][cpu]; if (!apr) { @@ -324,16 +341,25 @@ static void gic_drop_prio(GICState *s, int cpu, int g= roup) * running priority will be wrong, so interrupts that should preempt * might not do so, and interrupts that should not preempt might do so. */ - int i; + if (gic_is_vcpu(cpu)) { + int rcpu =3D gic_get_vcpu_real_id(cpu); =20 - for (i =3D 0; i < GIC_NR_APRS; i++) { - uint32_t *papr =3D group ? &s->nsapr[i][cpu] : &s->apr[i][cpu]; - if (!*papr) { - continue; + if (s->h_apr[rcpu]) { + /* Clear lowest set bit */ + s->h_apr[rcpu] &=3D s->h_apr[rcpu] - 1; + } + } else { + int i; + + for (i =3D 0; i < GIC_NR_APRS; i++) { + uint32_t *papr =3D group ? &s->nsapr[i][cpu] : &s->apr[i][cpu]; + if (!*papr) { + continue; + } + /* Clear lowest set bit */ + *papr &=3D *papr - 1; + break; } - /* Clear lowest set bit */ - *papr &=3D *papr - 1; - break; } =20 s->running_priority[cpu] =3D gic_get_prio_from_apr_bits(s, cpu); --=20 2.18.0