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[97.126.112.211]) by smtp.gmail.com with ESMTPSA id t21-v6sm2403258pfh.45.2018.07.09.10.56.05 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 09 Jul 2018 10:56:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Kr3nMz1r8DBHmbu7IkNk5Sue9fGLGjb64rBD+41zxWM=; b=SRjzX9QB/GNTi/8vYUk780J3sHzcWcTB5RMxWiFs5oVUgwjuGBGxbbvDJvgLAG6nho 1KBdRysGftI1PsbuQNdqUbbJnwLQDHhPCKdR0MM/hjavVOo1A3W9TiyjsF+AKhlY2xNq rK+k6sD1gRkw/nGUUa1M+zgKEJtEbBaaG/Fp8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Kr3nMz1r8DBHmbu7IkNk5Sue9fGLGjb64rBD+41zxWM=; b=GDW2N9SexxDdxluE1Y+xu5KEnpwgY4tER800P7O4rBMtEghZZI8ep87R7fO3hlbdTt Xy2K88b3mWsHmE3CtVDG99RH1rcztevQjAE5UhRMRn2CiXb/jpsUlukLGLVTocTTKL69 6//U5z9TUPIIfTvY/Luwv/GNDt4yt/+5840OhwZXKg2MXIExH9grPltHz/swgiqjON/r QN3P5H6r1QaWKZ5yUdlAQBhFVlXCux5d1ky/RE5MvVwCr3+uV9RUFo/XvFaldKgKjdCX +52f+vMt/Fgc5kckLi2Om3CmcUkTuecpE6TiSMYFRuz8TbsgL8GNhMC5tKbwyPPoD3TG +Iew== X-Gm-Message-State: APt69E0ZT0AhI6EX0/Lfk5KKbl7PkQLWxGwrCC/f2K+1j0VTsBac5Jih o5s4k1slwJD1B4NyhkuZFRQ4oxBXBnU= X-Google-Smtp-Source: AAOMgpcWAzpjKzvNFHtVVSM+didkWBm5u+f8GWycP+MCyLxSK3NCMQBlUoE/fMKGF0As3EIp+vvUGA== X-Received: by 2002:a63:1513:: with SMTP id v19-v6mr18468103pgl.358.1531158967032; Mon, 09 Jul 2018 10:56:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 9 Jul 2018 10:56:03 -0700 Message-Id: <20180709175603.1320-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180709175603.1320-1-richard.henderson@linaro.org> References: <20180709175603.1320-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::234 Subject: [Qemu-devel] [PULL for-3.0 1/1] target/sh4: Fix translator.c assertion failure for gUSA X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 The translator loop does not allow the tb_start hook to set dc->base.is_jmp; the only hook allowed to do that is translate_insn. Split the work between init_disas_context where we validate the gUSA parameters, and translate_insn where we emit code. Tested-by: Alex Benn=C3=A9e Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- target/sh4/translate.c | 81 +++++++++++++++++++++++------------------- 1 file changed, 44 insertions(+), 37 deletions(-) diff --git a/target/sh4/translate.c b/target/sh4/translate.c index c716b74a0f..1b9a201d6d 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -1895,35 +1895,18 @@ static void decode_opc(DisasContext * ctx) any sequence via cpu_exec_step_atomic, we can recognize the "normal" sequences and transform them into atomic operations as seen by the host. */ -static int decode_gusa(DisasContext *ctx, CPUSH4State *env, int *pmax_insn= s) +static void decode_gusa(DisasContext *ctx, CPUSH4State *env) { uint16_t insns[5]; int ld_adr, ld_dst, ld_mop; int op_dst, op_src, op_opc; int mv_src, mt_dst, st_src, st_mop; TCGv op_arg; - uint32_t pc =3D ctx->base.pc_next; uint32_t pc_end =3D ctx->base.tb->cs_base; - int backup =3D sextract32(ctx->tbflags, GUSA_SHIFT, 8); int max_insns =3D (pc_end - pc) / 2; int i; =20 - if (pc !=3D pc_end + backup || max_insns < 2) { - /* This is a malformed gUSA region. Don't do anything special, - since the interpreter is likely to get confused. */ - ctx->envflags &=3D ~GUSA_MASK; - return 0; - } - - if (ctx->tbflags & GUSA_EXCLUSIVE) { - /* Regardless of single-stepping or the end of the page, - we must complete execution of the gUSA region while - holding the exclusive lock. */ - *pmax_insns =3D max_insns; - return 0; - } - /* The state machine below will consume only a few insns. If there are more than that in a region, fail now. */ if (max_insns > ARRAY_SIZE(insns)) { @@ -2140,7 +2123,6 @@ static int decode_gusa(DisasContext *ctx, CPUSH4State= *env, int *pmax_insns) /* * Emit the operation. */ - tcg_gen_insn_start(pc, ctx->envflags); switch (op_opc) { case -1: /* No operation found. Look for exchange pattern. */ @@ -2235,7 +2217,8 @@ static int decode_gusa(DisasContext *ctx, CPUSH4State= *env, int *pmax_insns) /* The entire region has been translated. */ ctx->envflags &=3D ~GUSA_MASK; ctx->base.pc_next =3D pc_end; - return max_insns; + ctx->base.num_insns +=3D max_insns - 1; + return; =20 fail: qemu_log_mask(LOG_UNIMP, "Unrecognized gUSA sequence %08x-%08x\n", @@ -2243,7 +2226,6 @@ static int decode_gusa(DisasContext *ctx, CPUSH4State= *env, int *pmax_insns) =20 /* Restart with the EXCLUSIVE bit set, within a TB run via cpu_exec_step_atomic holding the exclusive lock. */ - tcg_gen_insn_start(pc, ctx->envflags); ctx->envflags |=3D GUSA_EXCLUSIVE; gen_save_cpu_state(ctx, false); gen_helper_exclusive(cpu_env); @@ -2254,7 +2236,7 @@ static int decode_gusa(DisasContext *ctx, CPUSH4State= *env, int *pmax_insns) entire region consumed via ctx->base.pc_next so that it's immediate= ly available in the disassembly dump. */ ctx->base.pc_next =3D pc_end; - return 1; + ctx->base.num_insns +=3D max_insns - 1; } #endif =20 @@ -2262,19 +2244,39 @@ static void sh4_tr_init_disas_context(DisasContextB= ase *dcbase, CPUState *cs) { DisasContext *ctx =3D container_of(dcbase, DisasContext, base); CPUSH4State *env =3D cs->env_ptr; + uint32_t tbflags; int bound; =20 - ctx->tbflags =3D (uint32_t)ctx->base.tb->flags; - ctx->envflags =3D ctx->base.tb->flags & TB_FLAG_ENVFLAGS_MASK; - ctx->memidx =3D (ctx->tbflags & (1u << SR_MD)) =3D=3D 0 ? 1 : 0; + ctx->tbflags =3D tbflags =3D ctx->base.tb->flags; + ctx->envflags =3D tbflags & TB_FLAG_ENVFLAGS_MASK; + ctx->memidx =3D (tbflags & (1u << SR_MD)) =3D=3D 0 ? 1 : 0; /* We don't know if the delayed pc came from a dynamic or static branc= h, so assume it is a dynamic branch. */ ctx->delayed_pc =3D -1; /* use delayed pc from env pointer */ ctx->features =3D env->features; - ctx->has_movcal =3D (ctx->tbflags & TB_FLAG_PENDING_MOVCA); - ctx->gbank =3D ((ctx->tbflags & (1 << SR_MD)) && - (ctx->tbflags & (1 << SR_RB))) * 0x10; - ctx->fbank =3D ctx->tbflags & FPSCR_FR ? 0x10 : 0; + ctx->has_movcal =3D (tbflags & TB_FLAG_PENDING_MOVCA); + ctx->gbank =3D ((tbflags & (1 << SR_MD)) && + (tbflags & (1 << SR_RB))) * 0x10; + ctx->fbank =3D tbflags & FPSCR_FR ? 0x10 : 0; + + if (tbflags & GUSA_MASK) { + uint32_t pc =3D ctx->base.pc_next; + uint32_t pc_end =3D ctx->base.tb->cs_base; + int backup =3D sextract32(ctx->tbflags, GUSA_SHIFT, 8); + int max_insns =3D (pc_end - pc) / 2; + + if (pc !=3D pc_end + backup || max_insns < 2) { + /* This is a malformed gUSA region. Don't do anything special, + since the interpreter is likely to get confused. */ + ctx->envflags &=3D ~GUSA_MASK; + } else if (tbflags & GUSA_EXCLUSIVE) { + /* Regardless of single-stepping or the end of the page, + we must complete execution of the gUSA region while + holding the exclusive lock. */ + ctx->base.max_insns =3D max_insns; + return; + } + } =20 /* Since the ISA is fixed-width, we can bound by the number of instructions remaining on the page. */ @@ -2284,14 +2286,6 @@ static void sh4_tr_init_disas_context(DisasContextBa= se *dcbase, CPUState *cs) =20 static void sh4_tr_tb_start(DisasContextBase *dcbase, CPUState *cs) { -#ifdef CONFIG_USER_ONLY - DisasContext *ctx =3D container_of(dcbase, DisasContext, base); - CPUSH4State *env =3D cs->env_ptr; - - if (ctx->tbflags & GUSA_MASK) { - ctx->base.num_insns =3D decode_gusa(ctx, env, &ctx->base.max_insns= ); - } -#endif } =20 static void sh4_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) @@ -2323,6 +2317,19 @@ static void sh4_tr_translate_insn(DisasContextBase *= dcbase, CPUState *cs) CPUSH4State *env =3D cs->env_ptr; DisasContext *ctx =3D container_of(dcbase, DisasContext, base); =20 +#ifdef CONFIG_USER_ONLY + if (unlikely(ctx->envflags & GUSA_MASK) + && !(ctx->envflags & GUSA_EXCLUSIVE)) { + /* We're in an gUSA region, and we have not already fallen + back on using an exclusive region. Attempt to parse the + region into a single supported atomic operation. Failure + is handled within the parser by raising an exception to + retry using an exclusive region. */ + decode_gusa(ctx, env); + return; + } +#endif + ctx->opcode =3D cpu_lduw_code(env, ctx->base.pc_next); decode_opc(ctx); ctx->base.pc_next +=3D 2; --=20 2.17.1