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From: Alistair Francis To: qemu-devel@nongnu.org, peter.maydell@linaro.org, mjc@sifive.com Date: Thu, 5 Jul 2018 18:22:09 -0700 Message-Id: <20180706012215.21714-2-alistair.francis@wdc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180706012215.21714-1-alistair.francis@wdc.com> References: <20180706012215.21714-1-alistair.francis@wdc.com> MIME-Version: 1.0 X-Originating-IP: [199.255.44.171] X-ClientProxiedBy: CO1PR15CA0105.namprd15.prod.outlook.com (2603:10b6:101:21::25) To CY4PR04MB0393.namprd04.prod.outlook.com (2603:10b6:903:b1::18) X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 999602ac-d60e-4bc1-7a40-08d5e2deef95 X-MS-Office365-Filtering-HT: Tenant X-Microsoft-Antispam: UriScan:; BCL:0; PCL:0; RULEID:(7020095)(4652040)(8989117)(5600053)(711020)(48565401081)(4534165)(4627221)(201703031133081)(201702281549075)(8990107)(2017052603328)(7153060)(7193020); SRVR:CY4PR04MB0393; X-Microsoft-Exchange-Diagnostics: 1; CY4PR04MB0393; 3:M9Id32hn8Nlj5w4Npj5oekTA7p70KyAoRlTe9lx3KcvGaDtF9K8uKeSKgmT/Kn9oc1D/HcowNsosB2do+LlMRZM80QQoDoLTTHTlitAzxAqXQLNmsnfhEamCioXOK9XWWz351f261jdb9sgB0AWOHtMxknuHfifLToCv+MovQ0Bdh22+MQwLO9/sDe7PJDmCyg+hplLsQVB7aqLfHi1cnHrgssh9OPhSxMaqbaMRG0hIzlqa7i5Xd2WuEVx2uPN6; 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X-Received-From: 216.71.154.45 Subject: [Qemu-devel] [PULL v4 1/7] hw/riscv/sifive_u: Create a SiFive U SoC object X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, Alistair Francis , f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (found 2 invalid signatures) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Create a SiFive Unleashed U54 SoC and use that in the sifive_u machine. We leave the SoC, RAM, device tree and reset/fdt loading as part of the machine. All the other device creation has been moved to the SoC. Signed-off-by: Alistair Francis Reviewed-by: Michael Clark --- hw/riscv/sifive_u.c | 87 +++++++++++++++++++++++++++---------- include/hw/riscv/sifive_u.h | 16 ++++++- 2 files changed, 79 insertions(+), 24 deletions(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index c05dcbba95..e2b4f97b10 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -116,10 +116,10 @@ static void create_fdt(SiFiveUState *s, const struct = MemmapEntry *memmap, qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0); qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1); =20 - for (cpu =3D s->soc.num_harts - 1; cpu >=3D 0; cpu--) { + for (cpu =3D s->soc.cpus.num_harts - 1; cpu >=3D 0; cpu--) { nodename =3D g_strdup_printf("/cpus/cpu@%d", cpu); char *intc =3D g_strdup_printf("/cpus/cpu@%d/interrupt-controller"= , cpu); - char *isa =3D riscv_isa_string(&s->soc.harts[cpu]); + char *isa =3D riscv_isa_string(&s->soc.cpus.harts[cpu]); qemu_fdt_add_subnode(fdt, nodename); qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", SIFIVE_U_CLOCK_FREQ); @@ -140,8 +140,8 @@ static void create_fdt(SiFiveUState *s, const struct Me= mmapEntry *memmap, g_free(nodename); } =20 - cells =3D g_new0(uint32_t, s->soc.num_harts * 4); - for (cpu =3D 0; cpu < s->soc.num_harts; cpu++) { + cells =3D g_new0(uint32_t, s->soc.cpus.num_harts * 4); + for (cpu =3D 0; cpu < s->soc.cpus.num_harts; cpu++) { nodename =3D g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); uint32_t intc_phandle =3D qemu_fdt_get_phandle(fdt, nodename); @@ -159,12 +159,12 @@ static void create_fdt(SiFiveUState *s, const struct = MemmapEntry *memmap, 0x0, memmap[SIFIVE_U_CLINT].base, 0x0, memmap[SIFIVE_U_CLINT].size); qemu_fdt_setprop(fdt, nodename, "interrupts-extended", - cells, s->soc.num_harts * sizeof(uint32_t) * 4); + cells, s->soc.cpus.num_harts * sizeof(uint32_t) * 4); g_free(cells); g_free(nodename); =20 - cells =3D g_new0(uint32_t, s->soc.num_harts * 4); - for (cpu =3D 0; cpu < s->soc.num_harts; cpu++) { + cells =3D g_new0(uint32_t, s->soc.cpus.num_harts * 4); + for (cpu =3D 0; cpu < s->soc.cpus.num_harts; cpu++) { nodename =3D g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); uint32_t intc_phandle =3D qemu_fdt_get_phandle(fdt, nodename); @@ -181,7 +181,7 @@ static void create_fdt(SiFiveUState *s, const struct Me= mmapEntry *memmap, qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0"); qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0); qemu_fdt_setprop(fdt, nodename, "interrupts-extended", - cells, s->soc.num_harts * sizeof(uint32_t) * 4); + cells, s->soc.cpus.num_harts * sizeof(uint32_t) * 4); qemu_fdt_setprop_cells(fdt, nodename, "reg", 0x0, memmap[SIFIVE_U_PLIC].base, 0x0, memmap[SIFIVE_U_PLIC].size); @@ -217,17 +217,12 @@ static void riscv_sifive_u_init(MachineState *machine) SiFiveUState *s =3D g_new0(SiFiveUState, 1); MemoryRegion *system_memory =3D get_system_memory(); MemoryRegion *main_mem =3D g_new(MemoryRegion, 1); - MemoryRegion *mask_rom =3D g_new(MemoryRegion, 1); int i; =20 - /* Initialize SOC */ - object_initialize(&s->soc, sizeof(s->soc), TYPE_RISCV_HART_ARRAY); + /* Initialize SoC */ + object_initialize(&s->soc, sizeof(s->soc), TYPE_RISCV_U_SOC); object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc), &error_abort); - object_property_set_str(OBJECT(&s->soc), SIFIVE_U_CPU, "cpu-type", - &error_abort); - object_property_set_int(OBJECT(&s->soc), smp_cpus, "num-harts", - &error_abort); object_property_set_bool(OBJECT(&s->soc), true, "realized", &error_abort); =20 @@ -235,17 +230,11 @@ static void riscv_sifive_u_init(MachineState *machine) memory_region_init_ram(main_mem, NULL, "riscv.sifive.u.ram", machine->ram_size, &error_fatal); memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DRAM].base, - main_mem); + main_mem); =20 /* create device tree */ create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline); =20 - /* boot rom */ - memory_region_init_rom(mask_rom, NULL, "riscv.sifive.u.mrom", - memmap[SIFIVE_U_MROM].size, &error_fatal); - memory_region_add_subregion(system_memory, memmap[SIFIVE_U_MROM].base, - mask_rom); - if (machine->kernel_filename) { load_kernel(machine->kernel_filename); } @@ -284,6 +273,36 @@ static void riscv_sifive_u_init(MachineState *machine) rom_add_blob_fixed_as("mrom.fdt", s->fdt, fdt_totalsize(s->fdt), memmap[SIFIVE_U_MROM].base + sizeof(reset_vec), &address_space_memory); +} + +static void riscv_sifive_u_soc_init(Object *obj) +{ + SiFiveUSoCState *s =3D RISCV_U_SOC(obj); + + object_initialize(&s->cpus, sizeof(s->cpus), TYPE_RISCV_HART_ARRAY); + object_property_add_child(obj, "cpus", OBJECT(&s->cpus), + &error_abort); + object_property_set_str(OBJECT(&s->cpus), SIFIVE_U_CPU, "cpu-type", + &error_abort); + object_property_set_int(OBJECT(&s->cpus), smp_cpus, "num-harts", + &error_abort); +} + +static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp) +{ + SiFiveUSoCState *s =3D RISCV_U_SOC(dev); + const struct MemmapEntry *memmap =3D sifive_u_memmap; + MemoryRegion *system_memory =3D get_system_memory(); + MemoryRegion *mask_rom =3D g_new(MemoryRegion, 1); + + object_property_set_bool(OBJECT(&s->cpus), true, "realized", + &error_abort); + + /* boot rom */ + memory_region_init_rom(mask_rom, NULL, "riscv.sifive.u.mrom", + memmap[SIFIVE_U_MROM].size, &error_fatal); + memory_region_add_subregion(system_memory, memmap[SIFIVE_U_MROM].base, + mask_rom); =20 /* MMIO */ s->plic =3D sifive_plic_create(memmap[SIFIVE_U_PLIC].base, @@ -314,3 +333,27 @@ static void riscv_sifive_u_machine_init(MachineClass *= mc) } =20 DEFINE_MACHINE("sifive_u", riscv_sifive_u_machine_init) + +static void riscv_sifive_u_soc_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(oc); + + dc->realize =3D riscv_sifive_u_soc_realize; + /* Reason: Uses serial_hds in realize function, thus can't be used twi= ce */ + dc->user_creatable =3D false; +} + +static const TypeInfo riscv_sifive_u_soc_type_info =3D { + .name =3D TYPE_RISCV_U_SOC, + .parent =3D TYPE_DEVICE, + .instance_size =3D sizeof(SiFiveUSoCState), + .instance_init =3D riscv_sifive_u_soc_init, + .class_init =3D riscv_sifive_u_soc_class_init, +}; + +static void riscv_sifive_u_soc_register_types(void) +{ + type_register_static(&riscv_sifive_u_soc_type_info); +} + +type_init(riscv_sifive_u_soc_register_types) diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index 94a390566e..49f1946539 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -19,13 +19,25 @@ #ifndef HW_SIFIVE_U_H #define HW_SIFIVE_U_H =20 -typedef struct SiFiveUState { +#define TYPE_RISCV_U_SOC "riscv.sifive.u.soc" +#define RISCV_U_SOC(obj) \ + OBJECT_CHECK(SiFiveUSoCState, (obj), TYPE_RISCV_U_SOC) + +typedef struct SiFiveUSoCState { /*< private >*/ SysBusDevice parent_obj; =20 /*< public >*/ - RISCVHartArrayState soc; + RISCVHartArrayState cpus; DeviceState *plic; +} SiFiveUSoCState; + +typedef struct SiFiveUState { + /*< private >*/ + SysBusDevice parent_obj; + + /*< public >*/ + SiFiveUSoCState soc; void *fdt; int fdt_size; } SiFiveUState; --=20 2.17.1