From nobody Tue Feb 10 15:01:17 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 15308275842571004.6702387075113; Thu, 5 Jul 2018 14:53:04 -0700 (PDT) Received: from localhost ([::1]:54936 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fbCBN-00012z-Jv for importer@patchew.org; Thu, 05 Jul 2018 17:52:57 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36136) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fbC9u-0000PW-Gh for qemu-devel@nongnu.org; Thu, 05 Jul 2018 17:51:27 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fbC9t-0000Bd-Ev for qemu-devel@nongnu.org; Thu, 05 Jul 2018 17:51:26 -0400 Received: from smtp39.i.mail.ru ([94.100.177.99]:52184) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1fbC9t-0000Ao-6x for qemu-devel@nongnu.org; Thu, 05 Jul 2018 17:51:25 -0400 Received: by smtp39.i.mail.ru with esmtpa (envelope-from ) id 1fbC9r-0007IQ-Bv; Fri, 06 Jul 2018 00:51:23 +0300 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mail.ru; s=mail2; h=References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From; bh=s+fiXGnalHenHQl4j9Q422jPCmwUb9Alw5NtoImnrTA=; b=qX1e/vo3cvTQGfVlLLzYebe0PXLi/Tl9ijLLv34hUwgtfX1C/43KnGLYpExHQ72GoFviJ+Ekj/2Ie1ssWXzS0+OibErGGmNjenZEgP6lc7VPWz4DgZmP6WdqyfCbEe4Bo6ej5uEbXfCOvbCJVqJRI2AEtvjGzw7Zsvf30pc1/ew=; To: qemu-devel@nongnu.org Date: Fri, 6 Jul 2018 00:50:51 +0300 Message-Id: <20180705215052.8795-2-jusual@mail.ru> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180705215052.8795-1-jusual@mail.ru> References: <20180705215052.8795-1-jusual@mail.ru> Authentication-Results: smtp39.i.mail.ru; auth=pass smtp.auth=jusual@mail.ru smtp.mailfrom=jusual@mail.ru X-7FA49CB5: 0D63561A33F958A5A59AADB719A462C05E321A400C02D8AB27A7CEBB1F2374560A6AB1C7CE11FEE3EB7D890E3377C531BA3038C0950A5D36B5C8C57E37DE458B4C7702A67D5C33162DBA43225CD8A89F0A35B161A8BF67C17E36F3CF6B04B741B422391175ED3B6043847C11F186F3C5E7DDDDC251EA7DABCC89B49CDF41148F458B267F216095A92623479134186CDE6BA297DBC24807EABDAD6C7F3747799A X-Mailru-Sender: 7766D515518070DE138AAC7428EA760DF19BD508F76C95C36A8B6EAF93AC8EBEA2696B57CA31463D7C4160E8B47E48163DDE9B364B0DF2898CB68AF7A628805D594FB4C9F0DBF412AE208404248635DF X-Mras: OK X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 94.100.177.99 Subject: [Qemu-devel] [PATCH v2 1/2] nvic: Handle ARMv6-M SCS reserved registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , From: Julia Suvorova via Qemu-devel Reply-To: Julia Suvorova Cc: Peter Maydell , Jim Mussared , =?UTF-8?q?Steffen=20G=C3=B6rtz?= , Joel Stanley , Stefan Hajnoczi , Julia Suvorova Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Handle SCS reserved registers listed in ARMv6-M ARM D3.6.1. All reserved registers are RAZ/WI. ARM_FEATURE_M_MAIN is used for the checks, because these registers are reserved in ARMv8-M Baseline too. Signed-off-by: Julia Suvorova --- hw/intc/armv7m_nvic.c | 51 +++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 49 insertions(+), 2 deletions(-) diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index aba4510c70..7f71b336bd 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -865,6 +865,9 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offse= t, MemTxAttrs attrs) } return val; case 0xd10: /* System Control. */ + if (!arm_feature(&cpu->env, ARM_FEATURE_V7)) { + goto bad_offset; + } return cpu->env.v7m.scr[attrs.secure]; case 0xd14: /* Configuration Control. */ /* The BFHFNMIGN bit is the only non-banked bit; we @@ -986,12 +989,21 @@ static uint32_t nvic_readl(NVICState *s, uint32_t off= set, MemTxAttrs attrs) } return val; case 0xd2c: /* Hard Fault Status. */ + if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { + goto bad_offset; + } return cpu->env.v7m.hfsr; case 0xd30: /* Debug Fault Status. */ return cpu->env.v7m.dfsr; case 0xd34: /* MMFAR MemManage Fault Address */ + if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { + goto bad_offset; + } return cpu->env.v7m.mmfar[attrs.secure]; case 0xd38: /* Bus Fault Address. */ + if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { + goto bad_offset; + } return cpu->env.v7m.bfar; case 0xd3c: /* Aux Fault Status. */ /* TODO: Implement fault status registers. */ @@ -1287,6 +1299,9 @@ static void nvic_writel(NVICState *s, uint32_t offset= , uint32_t value, } break; case 0xd10: /* System Control. */ + if (!arm_feature(&cpu->env, ARM_FEATURE_V7)) { + goto bad_offset; + } /* We don't implement deep-sleep so these bits are RAZ/WI. * The other bits in the register are banked. * QEMU's implementation ignores SEVONPEND and SLEEPONEXIT, which @@ -1388,15 +1403,24 @@ static void nvic_writel(NVICState *s, uint32_t offs= et, uint32_t value, nvic_irq_update(s); break; case 0xd2c: /* Hard Fault Status. */ + if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { + goto bad_offset; + } cpu->env.v7m.hfsr &=3D ~value; /* W1C */ break; case 0xd30: /* Debug Fault Status. */ cpu->env.v7m.dfsr &=3D ~value; /* W1C */ break; case 0xd34: /* Mem Manage Address. */ + if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { + goto bad_offset; + } cpu->env.v7m.mmfar[attrs.secure] =3D value; return; case 0xd38: /* Bus Fault Address. */ + if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { + goto bad_offset; + } cpu->env.v7m.bfar =3D value; return; case 0xd3c: /* Aux Fault Status. */ @@ -1626,6 +1650,11 @@ static void nvic_writel(NVICState *s, uint32_t offse= t, uint32_t value, case 0xf00: /* Software Triggered Interrupt Register */ { int excnum =3D (value & 0x1ff) + NVIC_FIRST_IRQ; + + if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { + goto bad_offset; + } + if (excnum < s->num_irq) { armv7m_nvic_set_pending(s, excnum, false); } @@ -1775,7 +1804,13 @@ static MemTxResult nvic_sysreg_read(void *opaque, hw= addr addr, } } break; - case 0xd18 ... 0xd23: /* System Handler Priority (SHPR1, SHPR2, SHPR3)= */ + case 0xd18: /* System Handler Priority (SHPR1) */ + if (!arm_feature(&s->cpu->env, ARM_FEATURE_M_MAIN)) { + val =3D 0; + break; + } + /* fall through */ + case 0xd1c ... 0xd23: /* System Handler Priority (SHPR2, SHPR3) */ val =3D 0; for (i =3D 0; i < size; i++) { unsigned hdlidx =3D (offset - 0xd14) + i; @@ -1788,6 +1823,10 @@ static MemTxResult nvic_sysreg_read(void *opaque, hw= addr addr, } break; case 0xd28 ... 0xd2b: /* Configurable Fault Status (CFSR) */ + if (!arm_feature(&s->cpu->env, ARM_FEATURE_M_MAIN)) { + val =3D 0; + break; + }; /* The BFSR bits [15:8] are shared between security states * and we store them in the NS copy */ @@ -1882,7 +1921,12 @@ static MemTxResult nvic_sysreg_write(void *opaque, h= waddr addr, } nvic_irq_update(s); return MEMTX_OK; - case 0xd18 ... 0xd23: /* System Handler Priority (SHPR1, SHPR2, SHPR3)= */ + case 0xd18: /* System Handler Priority (SHPR1) */ + if (!arm_feature(&s->cpu->env, ARM_FEATURE_M_MAIN)) { + return MEMTX_OK; + } + /* fall through */ + case 0xd1c ... 0xd23: /* System Handler Priority (SHPR2, SHPR3) */ for (i =3D 0; i < size; i++) { unsigned hdlidx =3D (offset - 0xd14) + i; int newprio =3D extract32(value, i * 8, 8); @@ -1896,6 +1940,9 @@ static MemTxResult nvic_sysreg_write(void *opaque, hw= addr addr, nvic_irq_update(s); return MEMTX_OK; case 0xd28 ... 0xd2b: /* Configurable Fault Status (CFSR) */ + if (!arm_feature(&s->cpu->env, ARM_FEATURE_M_MAIN)) { + return MEMTX_OK; + } /* All bits are W1C, so construct 32 bit value with 0s in * the parts not written by the access size */ --=20 2.17.1