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X-Received-From: 2607:f8b0:4001:c06::241 Subject: [Qemu-devel] [RFC] fix setting FPSCR[FR] bit X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: John Arbuckle Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" https://www.pdfdrive.net/powerpc-microprocessor-family-the-programming-envi= ronments-for-32-e3087633.html Page 63 in table 2-4 is where the description of this bit can be found. It is described as: Floating-point fraction rounded. The last arithmetic or rounding and conver= sion instruction that rounded the intermediate result incremented the fract= ion. This bit is NOT sticky. What I think this means is when the softfloat.c:round_canonical() function = adds the inc variable to the frac variable, the floating point fraction rou= nded bit should be set. It also means that every time a floating point oper= ation takes place, this bit needs to be updated since it isn't a sticky bit= . My testing has produced mixed results with this patch. Some of my floatin= g point tests are fixed by this patch, and others are broken by this patch.= I'm not clear if this is the right way to implement setting the FPSCR[FR] = bit. Feedback would be great. Signed-off-by: John Arbuckle --- fpu/softfloat.c | 6 +++++- include/fpu/softfloat-types.h | 1 + target/ppc/fpu_helper.c | 8 ++++++++ 3 files changed, 14 insertions(+), 1 deletion(-) diff --git a/fpu/softfloat.c b/fpu/softfloat.c index 8cd2400081..b2b2c61cff 100644 --- a/fpu/softfloat.c +++ b/fpu/softfloat.c @@ -382,11 +382,12 @@ static FloatParts round_canonical(FloatParts p, float= _status *s, const uint64_t roundeven_mask =3D parm->roundeven_mask; const int exp_max =3D parm->exp_max; const int frac_shift =3D parm->frac_shift; - uint64_t frac, inc; + uint64_t frac, inc, old_frac; int exp, flags =3D 0; bool overflow_norm; =20 frac =3D p.frac; + old_frac =3D frac; /* Used to determine if the fraction was rounded */ exp =3D p.exp; =20 switch (p.cls) { @@ -503,6 +504,9 @@ static FloatParts round_canonical(FloatParts p, float_s= tatus *s, g_assert_not_reached(); } =20 + if (frac !=3D old_frac) { + flags |=3D float_flag_round; + } float_raise(flags, s); p.exp =3D exp; p.frac =3D frac; diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h index 2aae6a89b1..1d124e659c 100644 --- a/include/fpu/softfloat-types.h +++ b/include/fpu/softfloat-types.h @@ -147,6 +147,7 @@ enum { =20 enum { float_flag_invalid =3D 1, + float_flag_round =3D 2, float_flag_divbyzero =3D 4, float_flag_overflow =3D 8, float_flag_underflow =3D 16, diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index cb82e6e842..ba57ea7cfe 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -581,6 +581,7 @@ static void do_float_check_status(CPUPPCState *env, uin= tptr_t raddr) CPUState *cs =3D CPU(ppc_env_get_cpu(env)); int status =3D get_float_exception_flags(&env->fp_status); bool inexact_happened =3D false; + bool round_happened =3D false; =20 if (status & float_flag_overflow) { float_overflow_excp(env); @@ -589,6 +590,8 @@ static void do_float_check_status(CPUPPCState *env, uin= tptr_t raddr) } else if (status & float_flag_inexact) { float_inexact_excp(env); inexact_happened =3D true; + } else if (status & float_flag_round) { + round_happened =3D true; } =20 /* if the inexact flag was not set */ @@ -596,6 +599,11 @@ static void do_float_check_status(CPUPPCState *env, ui= ntptr_t raddr) env->fpscr &=3D ~(1 << FPSCR_FI); /* clear the FPSCR[FI] bit */ } =20 + /* if the floating-point fraction rounded bit was not set */ + if (round_happened =3D=3D false) { + env->fpscr &=3D ~(1 << FPSCR_FR); /* clear the FPSCR[FR] bit */ + } + if (cs->exception_index =3D=3D POWERPC_EXCP_PROGRAM && (env->error_code & POWERPC_EXCP_FP)) { /* Differred floating-point exception after target FPR update */ --=20 2.14.3 (Apple Git-98)