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[97.126.112.211]) by smtp.gmail.com with ESMTPSA id s185-v6sm4834201pfb.116.2018.07.03.08.17.43 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 03 Jul 2018 08:17:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=m+eauDzkbLO8Pb2FKzAIybKR1kdYA2iqGOrOBkGxKK4=; b=B5rGs70Sk7Gw9OC8cwZcVZGU1+fQm3F69JhCioDp3eMVSRwasiEttbr7ggGWKar81+ RQ3gJxGIvsEeV0mNv52FdKwHNUfc77dNSNOoWqE3mbvdJdiI7cypue/0uOaF8xuCatNq HtKCAdK/UWEHFYLx0LCR7k6AG463UGeRb2+wM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=m+eauDzkbLO8Pb2FKzAIybKR1kdYA2iqGOrOBkGxKK4=; b=lQj/EP0tG2pu1CBUapdGxxk5Ad2YSHipdK9yROrgOn7YT+KQNoRq8j6Ir+rTz6oFxa oH+ptjISSi31UsdlWUEa1lxHjp0O+DZTxk9FWSSl5InXnaP3yUhwxuO8OV9neufR/XBx Pxd2GE3VaVQTjWPHvvlNXOm3+GSyS2Co7xRNs67bhSGzJ1jGqW/Iw6eNAZHiW72IEq5n Zsz0WHiaDRT/7xTVFhSw9Zo/K7VNTatGg3ZOQQxZDDZP33n/cRVF8Wr15HRy13xK64XP L1oyY7/fAOdmHNydWIPIJueK9Ygn+CXtcIFvSmMoD77j47O6tipbh8etwF7DFVwk9Ypw jMzQ== X-Gm-Message-State: APt69E3IeURpPNrMBwpGl7TfmTDLfTPT5Ca7aRHZJ5zLYjDx7zP/WjCe SJkOEMDai/kQuN4WZCE4bw3q4e0Xttw= X-Google-Smtp-Source: AAOMgpcOSOlEdbNmiRPBO3g2BZUYYiqwMdOQbSrmXDsxkpqH524N9j2Im7oRU5lon70vIYyC6ssqvQ== X-Received: by 2002:a63:161a:: with SMTP id w26-v6mr5252151pgl.257.1530631065339; Tue, 03 Jul 2018 08:17:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 3 Jul 2018 08:17:32 -0700 Message-Id: <20180703151732.29843-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180703151732.29843-1-richard.henderson@linaro.org> References: <20180703151732.29843-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::22e Subject: [Qemu-devel] [PATCH 7/7] target/ppc: Use non-arithmetic conversions for fp load/store X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: programmingkidx@gmail.com, qemu-ppc@nongnu.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Memory operations have no side effects on fp state. The use of a "real" conversions between float64 and float32 would raise exceptions for SNaN and out-of-range inputs. Signed-off-by: Richard Henderson --- target/ppc/helper.h | 4 +- target/ppc/fpu_helper.c | 63 ++++++++++++++++++++++++------ target/ppc/translate/fp-impl.inc.c | 26 +++++------- 3 files changed, 62 insertions(+), 31 deletions(-) diff --git a/target/ppc/helper.h b/target/ppc/helper.h index cc3d031407..33e6e1df60 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -61,8 +61,8 @@ DEF_HELPER_2(compute_fprf_float64, void, env, i64) DEF_HELPER_3(store_fpscr, void, env, i64, i32) DEF_HELPER_2(fpscr_clrbit, void, env, i32) DEF_HELPER_2(fpscr_setbit, void, env, i32) -DEF_HELPER_2(float64_to_float32, i32, env, i64) -DEF_HELPER_2(float32_to_float64, i64, env, i32) +DEF_HELPER_FLAGS_1(todouble, TCG_CALL_NO_RWG_SE, i64, i32) +DEF_HELPER_FLAGS_1(tosingle, TCG_CALL_NO_RWG_SE, i32, i64) =20 DEF_HELPER_4(fcmpo, void, env, i64, i64, i32) DEF_HELPER_4(fcmpu, void, env, i64, i64, i32) diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index 1e195487d3..d4e9e3bccb 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -47,24 +47,61 @@ static inline bool fp_exceptions_enabled(CPUPPCState *e= nv) =20 /*************************************************************************= ****/ /* Floating point operations helpers */ -uint64_t helper_float32_to_float64(CPUPPCState *env, uint32_t arg) -{ - CPU_FloatU f; - CPU_DoubleU d; =20 - f.l =3D arg; - d.d =3D float32_to_float64(f.f, &env->fp_status); - return d.ll; +/* + * This is the non-arithmatic conversion that happens e.g. on loads. + * In the Power ISA pseudocode, this is called DOUBLE. + */ +uint64_t helper_todouble(uint32_t arg) +{ + uint32_t abs_arg =3D arg & 0x7fffffff; + uint64_t ret; + + if (likely(abs_arg >=3D 0x00800000)) { + /* Normalized operand, or Inf, or NaN. */ + ret =3D (uint64_t)extract32(arg, 30, 2) << 62; + ret |=3D ((extract32(arg, 30, 1) ^ 1) * (uint64_t)7) << 59; + ret |=3D (uint64_t)extract32(arg, 0, 29) << 29; + } else { + /* Zero or Denormalized operand. */ + ret =3D (uint64_t)extract32(arg, 31, 1) << 63; + if (unlikely(abs_arg !=3D 0)) { + /* Denormalized operand. */ + int shift =3D clz32(abs_arg) - 9; + int exp =3D -126 - shift + 1023; + ret |=3D (uint64_t)exp << 52; + ret |=3D abs_arg << (shift + 29); + } + } + return ret; } =20 -uint32_t helper_float64_to_float32(CPUPPCState *env, uint64_t arg) +/* + * This is the non-arithmatic conversion that happens e.g. on stores. + * In the Power ISA pseudocode, this is called SINGLE. + */ +uint32_t helper_tosingle(uint64_t arg) { - CPU_FloatU f; - CPU_DoubleU d; + int exp =3D extract64(arg, 52, 11); + uint32_t ret; =20 - d.ll =3D arg; - f.f =3D float64_to_float32(d.d, &env->fp_status); - return f.l; + if (likely(exp > 896)) { + /* No denormalization required (includes Inf, NaN). */ + ret =3D extract64(arg, 62, 2) << 30; + ret |=3D extract64(arg, 29, 29); + } else { + /* Zero or Denormal result. If the exponent is in bounds for + * a single-precision denormal result, extract the proper bits. + * If the input is not zero, and the exponent is out of bounds, + * then the result is undefined; this underflows to zero. + */ + ret =3D extract64(arg, 63, 1) << 63; + if (unlikely(exp >=3D 874)) { + /* Denormal result. */ + ret |=3D ((1ULL << 52) | extract64(arg, 0, 52)) >> (896 + 30 -= exp); + } + } + return ret; } =20 static inline int ppc_float32_get_unbiased_exp(float32 f) diff --git a/target/ppc/translate/fp-impl.inc.c b/target/ppc/translate/fp-i= mpl.inc.c index 2fbd4d4f38..a6f522b85c 100644 --- a/target/ppc/translate/fp-impl.inc.c +++ b/target/ppc/translate/fp-impl.inc.c @@ -660,15 +660,12 @@ GEN_LDUF(name, ldop, op | 0x21, type); = \ GEN_LDUXF(name, ldop, op | 0x01, type); = \ GEN_LDXF(name, ldop, 0x17, op | 0x00, type) =20 -static inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv = arg2) +static void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 dest, TCGv addr) { - TCGv t0 =3D tcg_temp_new(); - TCGv_i32 t1 =3D tcg_temp_new_i32(); - gen_qemu_ld32u(ctx, t0, arg2); - tcg_gen_trunc_tl_i32(t1, t0); - tcg_temp_free(t0); - gen_helper_float32_to_float64(arg1, cpu_env, t1); - tcg_temp_free_i32(t1); + TCGv_i32 tmp =3D tcg_temp_new_i32(); + tcg_gen_qemu_ld_i32(tmp, addr, ctx->mem_idx, DEF_MEMOP(MO_UL)); + gen_helper_todouble(dest, tmp); + tcg_temp_free_i32(tmp); } =20 /* lfd lfdu lfdux lfdx */ @@ -836,15 +833,12 @@ GEN_STUF(name, stop, op | 0x21, type); = \ GEN_STUXF(name, stop, op | 0x01, type); = \ GEN_STXF(name, stop, 0x17, op | 0x00, type) =20 -static inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv = arg2) +static void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 src, TCGv addr) { - TCGv_i32 t0 =3D tcg_temp_new_i32(); - TCGv t1 =3D tcg_temp_new(); - gen_helper_float64_to_float32(t0, cpu_env, arg1); - tcg_gen_extu_i32_tl(t1, t0); - tcg_temp_free_i32(t0); - gen_qemu_st32(ctx, t1, arg2); - tcg_temp_free(t1); + TCGv_i32 tmp =3D tcg_temp_new_i32(); + gen_helper_tosingle(tmp, src); + tcg_gen_qemu_st_i32(tmp, addr, ctx->mem_idx, DEF_MEMOP(MO_UL)); + tcg_temp_free_i32(tmp); } =20 /* stfd stfdu stfdux stfdx */ --=20 2.17.1