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[97.126.112.211]) by smtp.gmail.com with ESMTPSA id s185-v6sm4834201pfb.116.2018.07.03.08.17.42 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 03 Jul 2018 08:17:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=pH8EovXGz1h8tlGLK9DZKB5EE5L+qrmSbfLNiXlUNU0=; b=jLkjL8CUyEXFeVRhlE2Ajv/X5qXYJ9Lqq4w0WUK61PDYRxzMpm8hRwgPjKV3k1z+PR b2K+gx0DD2kZQGe3KwxEfPCQXgPACU2GHbNvA5m+YL2jx7/OmbvqoX6283VNVipx01BX QSNpZauAh35dBk34z02AKxepjH08DfJjqz2CE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=pH8EovXGz1h8tlGLK9DZKB5EE5L+qrmSbfLNiXlUNU0=; b=jSZ4wzPeVVvABIZJbNgH0FV5Jhkf130ndux6jfN8pZM7Zv4o1twap9AOTDGkVK/hFw Xk59USqG9GtUv/Ookvr4zan/7IFMxiHdeqz2UlVJdtMCdwCJiVM9CWpjtTT2TntzVuYd hAotRJcc/zhxSR5FOcgfIo/5XX4UIPJSCC++yUEZBlUHoK6ibwufyIAqKOYHogr++zpw k2qWjO2VUpKbSpoArjmuK2UIv70layCfERmqmwbxr+qbeAiI7HUTApqgl8AuVKRaQQpO NdOov6hK/8L8rM5WgNmn+9akY7EtBLCDlTTZB1LhBRQi3wjrOlJEXx9A61F3LXl5f5Iz HSiA== X-Gm-Message-State: APt69E0qqPKIWSsiDYQ1Pij3GKePW0cJDjTpUnnovWwAyblVT3zbDqRx t66Y+2aObn7hHbh9hlCTVn53nO4NYqQ= X-Google-Smtp-Source: ADUXVKKSceaODFpblqzUh/1Je5fLK2yQHMXAtC/sX6OEcHtZG6JEyq+j9MDc5wxsNHV1YeuojZ9geg== X-Received: by 2002:a63:4002:: with SMTP id n2-v6mr25398977pga.285.1530631063683; Tue, 03 Jul 2018 08:17:43 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 3 Jul 2018 08:17:31 -0700 Message-Id: <20180703151732.29843-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180703151732.29843-1-richard.henderson@linaro.org> References: <20180703151732.29843-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::242 Subject: [Qemu-devel] [PATCH 6/7] target/ppc: Honor fpscr_ze semantics and tidy fre, fresqrt X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: programmingkidx@gmail.com, qemu-ppc@nongnu.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Divide by zero, exception taken, leaves the destination register unmodified. Therefore we must raise the exception before returning from the respective helpers. From helper_fre, divide by zero exception not taken, return the documented +/- 0.5. At the same time, tidy the invalid exception checking so that we rely on softfloat for initial argument validation, and select the kind of invalid operand exception only when we know we must. At the same time, pass and return float64 values directly rather than bounce through the CPU_DoubleU union. Signed-off-by: Richard Henderson --- target/ppc/fpu_helper.c | 62 ++++++++++++++++++++++++----------------- 1 file changed, 37 insertions(+), 25 deletions(-) diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index c8a2dd6408..1e195487d3 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -871,18 +871,27 @@ float64 helper_fsqrt(CPUPPCState *env, float64 arg) } =20 /* fre - fre. */ -uint64_t helper_fre(CPUPPCState *env, uint64_t arg) +float64 helper_fre(CPUPPCState *env, float64 arg) { - CPU_DoubleU farg; + /* "Estimate" the reciprocal with actual division. */ + float64 ret =3D float64_div(float64_one, arg, &env->fp_status); + int status =3D get_float_exception_flags(&env->fp_status); =20 - farg.ll =3D arg; - - if (unlikely(float64_is_signaling_nan(farg.d, &env->fp_status))) { - /* sNaN reciprocal */ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1); + if (unlikely(status)) { + if (status & float_flag_invalid) { + if (float64_is_signaling_nan(arg, &env->fp_status)) { + /* sNaN reciprocal */ + float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1); + } + } + if (status & float_flag_divbyzero) { + float_zero_divide_excp(env, GETPC()); + /* For FPSCR.ZE =3D=3D 0, the result is 1/2. */ + ret =3D float64_set_sign(float64_half, float64_is_neg(arg)); + } } - farg.d =3D float64_div(float64_one, farg.d, &env->fp_status); - return farg.d; + + return ret; } =20 /* fres - fres. */ @@ -905,27 +914,30 @@ uint64_t helper_fres(CPUPPCState *env, uint64_t arg) } =20 /* frsqrte - frsqrte. */ -uint64_t helper_frsqrte(CPUPPCState *env, uint64_t arg) +float64 helper_frsqrte(CPUPPCState *env, float64 arg) { - CPU_DoubleU farg; + /* "Estimate" the reciprocal with actual division. */ + float64 rets =3D float64_sqrt(arg, &env->fp_status); + float64 retd =3D float64_div(float64_one, rets, &env->fp_status); + int status =3D get_float_exception_flags(&env->fp_status); =20 - farg.ll =3D arg; - - if (unlikely(float64_is_any_nan(farg.d))) { - if (unlikely(float64_is_signaling_nan(farg.d, &env->fp_status))) { - /* sNaN reciprocal square root */ - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1); - farg.ll =3D float64_snan_to_qnan(farg.ll); + if (unlikely(status)) { + if (status & float_flag_invalid) { + if (float64_is_signaling_nan(arg, &env->fp_status)) { + /* sNaN reciprocal */ + float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1); + } else { + /* Square root of a negative nonzero number */ + float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSQRT, 1); + } + } + if (status & float_flag_divbyzero) { + /* Reciprocal of (square root of) zero. */ + float_zero_divide_excp(env, GETPC()); } - } else if (unlikely(float64_is_neg(farg.d) && !float64_is_zero(farg.d)= )) { - /* Reciprocal square root of a negative nonzero number */ - farg.ll =3D float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSQRT, 1); - } else { - farg.d =3D float64_sqrt(farg.d, &env->fp_status); - farg.d =3D float64_div(float64_one, farg.d, &env->fp_status); } =20 - return farg.ll; + return retd; } =20 /* fsel - fsel. */ --=20 2.17.1