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[97.126.112.211]) by smtp.gmail.com with ESMTPSA id s185-v6sm4834201pfb.116.2018.07.03.08.17.39 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 03 Jul 2018 08:17:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=qjw75CxqESA4vzlkdFHX1h76eY2G0aFYSmt9TQ3Q/ag=; b=KfMi5xFUEE/A0X12QXE94M24kuOFIlBpvc+vwD8mu8Nqczl33LYtSVw20UT0lG64mW LunyyhFxKTiEvVJafCwfBCxo9PEnjCo6HxyoWT/Ngyb6h50luxljLfwCWQcqRzl1dUcU 09Fz+vdu9BRobNhPcvcTTSVbB82aMIGdAgZkU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=qjw75CxqESA4vzlkdFHX1h76eY2G0aFYSmt9TQ3Q/ag=; b=uckm2kG61LbK4or36c6kr8mh8iQpks9g5gDEug3VsSriKgHUgzX2kwp4KcZwYE8/kk NWEV7VDzh7t3dGs8uBg6nReMaKvmZE+5EXNdcrrPCFGPBq//b5L++8AaH1QZwtc3Dfhr KeInMtSWVOSibeFHogQKIk9gPofjGpAi0qLFcjdAJzOj/cS7g5+4xPY708AVXQCEtLjM kNz7wFMwj4QJbOtwTu4XIgVZk9M0wnBZCxk/BsdK3q+F4TOOwB7l/USYRMZhke0OPOWS qZv4SHyojlQ6SBKjO8EMAgJGCiyd0P1/XLNh2pYTPMI40FTnCMBfJDJGQG7ZPTtCq/zv Ogwg== X-Gm-Message-State: APt69E39Vm2LA9GLapvDRzL+GT23mW/8xlEjbe+7IEuGW0wmoalmBJmG 1gqMnWUro3l1Z0Ti8E0vQSiRA13cw0c= X-Google-Smtp-Source: AAOMgpfB7pONupng2bZTBollqri3NUPW7pyP6WlBJw9YnCRSLps5aTaYejrq4QkVVlYLQeFVId8Z7w== X-Received: by 2002:a63:5106:: with SMTP id f6-v6mr8476931pgb.95.1530631060463; Tue, 03 Jul 2018 08:17:40 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Tue, 3 Jul 2018 08:17:29 -0700 Message-Id: <20180703151732.29843-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180703151732.29843-1-richard.henderson@linaro.org> References: <20180703151732.29843-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c00::22f Subject: [Qemu-devel] [PATCH 4/7] target/ppc: Tidy helper_fadd, helper_fsub X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: programmingkidx@gmail.com, qemu-ppc@nongnu.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZohoMail: RDKM_2 RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Tidy the invalid exception checking so that we rely on softfloat for initial argument validation, and select the kind of invalid operand exception only when we know we must. Pass and return float64 values directly rather than bounce through the CPU_DoubleU union. Note that because we know float_flag_invalid was set, we do not have to re-check the signs of the infinities. Signed-off-by: Richard Henderson --- target/ppc/helper.h | 4 ++-- target/ppc/fpu_helper.c | 50 +++++++++++++++++------------------------ 2 files changed, 23 insertions(+), 31 deletions(-) diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 7ddbc0fc19..3262e2feaf 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -85,8 +85,8 @@ DEF_HELPER_2(friz, i64, env, i64) DEF_HELPER_2(frip, i64, env, i64) DEF_HELPER_2(frim, i64, env, i64) =20 -DEF_HELPER_3(fadd, i64, env, i64, i64) -DEF_HELPER_3(fsub, i64, env, i64, i64) +DEF_HELPER_3(fadd, f64, env, f64, f64) +DEF_HELPER_3(fsub, f64, env, f64, f64) DEF_HELPER_3(fmul, f64, env, f64, f64) DEF_HELPER_3(fdiv, f64, env, f64, f64) DEF_HELPER_4(fmadd, i64, env, i64, i64, i64) diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index 5642734b5b..2d56c93498 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -579,51 +579,43 @@ void helper_reset_fpstatus(CPUPPCState *env) } =20 /* fadd - fadd. */ -uint64_t helper_fadd(CPUPPCState *env, uint64_t arg1, uint64_t arg2) +float64 helper_fadd(CPUPPCState *env, float64 arg1, float64 arg2) { - CPU_DoubleU farg1, farg2; + float64 ret =3D float64_add(arg1, arg2, &env->fp_status); + int status =3D get_float_exception_flags(&env->fp_status); =20 - farg1.ll =3D arg1; - farg2.ll =3D arg2; - - if (unlikely(float64_is_infinity(farg1.d) && float64_is_infinity(farg2= .d) && - float64_is_neg(farg1.d) !=3D float64_is_neg(farg2.d))) { - /* Magnitude subtraction of infinities */ - farg1.ll =3D float_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI, 1); - } else { - if (unlikely(float64_is_signaling_nan(farg1.d, &env->fp_status) || - float64_is_signaling_nan(farg2.d, &env->fp_status))) { + if (unlikely(status & float_flag_invalid)) { + if (float64_is_infinity(arg1) && float64_is_infinity(arg2)) { + /* Magnitude subtraction of infinities */ + float_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI, 1); + } else if (float64_is_signaling_nan(arg1, &env->fp_status) || + float64_is_signaling_nan(arg2, &env->fp_status)) { /* sNaN addition */ float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1); } - farg1.d =3D float64_add(farg1.d, farg2.d, &env->fp_status); } =20 - return farg1.ll; + return ret; } =20 /* fsub - fsub. */ -uint64_t helper_fsub(CPUPPCState *env, uint64_t arg1, uint64_t arg2) +float64 helper_fsub(CPUPPCState *env, float64 arg1, float64 arg2) { - CPU_DoubleU farg1, farg2; + float64 ret =3D float64_sub(arg1, arg2, &env->fp_status); + int status =3D get_float_exception_flags(&env->fp_status); =20 - farg1.ll =3D arg1; - farg2.ll =3D arg2; - - if (unlikely(float64_is_infinity(farg1.d) && float64_is_infinity(farg2= .d) && - float64_is_neg(farg1.d) =3D=3D float64_is_neg(farg2.d))) { - /* Magnitude subtraction of infinities */ - farg1.ll =3D float_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI, 1); - } else { - if (unlikely(float64_is_signaling_nan(farg1.d, &env->fp_status) || - float64_is_signaling_nan(farg2.d, &env->fp_status))) { - /* sNaN subtraction */ + if (unlikely(status & float_flag_invalid)) { + if (float64_is_infinity(arg1) && float64_is_infinity(arg2)) { + /* Magnitude subtraction of infinities */ + float_invalid_op_excp(env, POWERPC_EXCP_FP_VXISI, 1); + } else if (float64_is_signaling_nan(arg1, &env->fp_status) || + float64_is_signaling_nan(arg2, &env->fp_status)) { + /* sNaN addition */ float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 1); } - farg1.d =3D float64_sub(farg1.d, farg2.d, &env->fp_status); } =20 - return farg1.ll; + return ret; } =20 /* fmul - fmul. */ --=20 2.17.1